Fast Simulation of Computer Architectures
β Scribed by Thomas M. Conte, Charles E. Gimarc (auth.), Thomas M. Conte, Charles E. Gimarc (eds.)
- Publisher
- Springer US
- Year
- 1995
- Tongue
- English
- Leaves
- 248
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
Chapters in Fast Simulation of Computer Architectures cover topics such as how to collect traces, emulate instruction sets, simulate microprocessors using execution-driven techniques, evaluate memory hierarchies, apply statistical sampling to simulation, and how to augment simulation with performance bound models. The chapters have been written by many of the leading researchers in the area, in a collaboration that ensures that the material is both coherent and cohesive.
Audience: Of tremendous interest to practising computer architect designers seeking timely solutions to tough evaluation problems, and to advanced upper division undergraduate and graduate students of the field. Useful study aids are provided by the problems at the end of Chapters 2 through 8.
β¦ Table of Contents
Front Matter....Pages i-ix
Introduction....Pages 1-4
Shade: A Fast Instruction-Set Simulator for Execution Profiling....Pages 5-46
Instrumentation Tools....Pages 47-86
Stack-Based Single-Pass Cache Simulation....Pages 87-107
Non-Stack Single-Pass Simulation....Pages 109-144
Execution Driven Simulation of Shared Memory Multiprocessors....Pages 145-170
Sampling for Cache and Processor Simulation....Pages 171-203
Performance Bounds for Rapid Computer System Evaluation....Pages 205-237
Back Matter....Pages 239-244
β¦ Subjects
Processor Architectures; Computer Systems Organization and Communication Networks
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