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Fast parallel-prefix modulo 2n+1 adders

✍ Scribed by Efstathiou, C.; Vergos, H.T.; Nikolos, D.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Modulo 2n±1 adder design using select-pr

✍ Efstathiou, C.; Vergos, H.T.; Nikolos, D. 📂 Article 📅 2003 🏛 IEEE 🌐 English ⚖ 923 KB

On the Design of Modulo 2n±1 Subtractors

✍ E. Vassalos; D. Bakalis; H. T. Vergos 📂 Article 📅 2011 🏛 Springer 🌐 English ⚖ 450 KB

Diminished-one modulo 2n+1 adder design

✍ Vergos, H.T.; Efstathiou, C.; Nikolos, D. 📂 Article 📅 2002 🏛 IEEE 🌐 English ⚖ 473 KB

Fast Modulo 2^{n} - (2^{n - 2} + 1) Addi

✍ Patel, R.A.; Benaissa, M.; Boussakta, S. 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 907 KB

Fast parallel prefix logic circuits for

✍ H. Fatih Ugurdag; Onur Baskirt 📂 Article 📅 2012 🏛 Elsevier Science 🌐 English ⚖ 907 KB

Modulo (2n+1) arithmetic logic

✍ Agrawal, Dharma P.; Rao, T.R.N. 📂 Article 📅 1978 🏛 Institution of Electrical Engineers ⚖ 310 KB