✦ LIBER ✦
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
✍ Scribed by Yu Hu; Shih, V.; Majumdar, R.; Lei He
- Book ID
- 117908000
- Publisher
- IEEE
- Year
- 2008
- Tongue
- English
- Weight
- 731 KB
- Volume
- 27
- Category
- Article
- ISSN
- 0278-0070
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