Embedded systems design based on formal models of computation

✍ Scribed by Radojevic, Ivan

• Publisher: Springer
• Year: 2012
• Tongue: English
• Leaves: 193
• Category: Library

✦ Synopsis

Introduction -- Models of computation and languages -- Specification in DFCharts -- Semantics of DFCharts -- DFCharts in systemC and esterel -- Java environment for DFCharts -- Heterogeneous reactive architectures of embedded systems -- Implementation of DFCharts on HiDRA -- Conclusions.

✦ Table of Contents

9.2.2 Hardware Implementation......Page 3
9.2.7 Proof of Correctness for DFCharts Implementation......Page 5
Index......Page 7
7.3.2 Power Aware ReMIC-PA......Page 11
8.2.4 FSM Scheduler......Page 15
Cover......Page 1
Embedded Systems Design Based on Formal Models of Computation......Page 4
Preface......Page 6
Contents......Page 8
8.2.2.2 States Visible in Specification......Page 10
7.4.1 An Overview of HiDRA......Page 14
1.1 Embedded Systems Design......Page 18
1.3 Book Organization......Page 22
2.10 Esterel......Page 23
2.11 Lustre and Signal......Page 27
4.2.1 Data Transfer from SDF to FSM......Page 28
2.5 Discrete Event Model......Page 31
6.2 SDFG Classes......Page 9
List of Figures......Page 12
8.2.3 Hierarchical and Parallel Compositions......Page 13
5.1.2.1 SystemC......Page 2
8.2.5 Master Tick Handler......Page 17
2.1 Finite State Machine......Page 24
2.2 Kahn Process Networks......Page 26
2.4 Synchronous/Reactive Model......Page 30
List of Tables......Page 16
6.6 Frequency Relay Revisited......Page 19
8.3 Frequency Relay Implementation......Page 20
1.2 DFCharts......Page 21
2.3 Synchronous Dataflow......Page 29
2.6 Communicating Sequential Processes......Page 33
2.7 Petri Nets......Page 37
2.8 Statecharts/Statemate......Page 41
2.9 Argos......Page 45
2.10 Esterel......Page 46
2.11 Lustre and Signal......Page 50
2.12 SystemC......Page 51
2.13 Ptolemy......Page 54
3.1.1 Operators......Page 59
3.1.2 Transition Priorities......Page 62
3.1.3 Variables......Page 63
3.1.4 Data Transfer Between FSM and SDF......Page 65
3.2 Case Study: Frequency Relay......Page 66
3.2.1 Peak Detection......Page 67
3.2.2 Frequency and Rate of Change Calculations......Page 68
3.2.3 Switch Control......Page 69
3.2.4 Threshold Modification......Page 70
3.3 DDFCharts......Page 71
3.4 Frequency Relay Extension......Page 73
Chapter 4: Semantics of DFCharts......Page 76
4.1 Automata Semantics......Page 77
4.1.1 FSM with Variables......Page 81
4.1.2 Synchronous Parallel Operator......Page 85
4.1.3 Asynchronous Parallel Operator......Page 88
4.1.4 Hiding Operator......Page 92
4.1.5 Refinement Operator......Page 93
4.1.6 Mapping Syntax to Automata......Page 97
4.1.7 Integrating SDF Graphs into Automata Semantics......Page 99
4.2 TSM Semantics......Page 101
4.2.1 Data Transfer from SDF to FSM......Page 103
4.2.2 Data Transfer from FSM to SDF......Page 105
4.3 The Impact of Clock Speeds......Page 106
5.1 Analysis Based on Requirements......Page 108
5.1.1.1 SystemC......Page 109
5.1.3.1 SystemC......Page 110
5.1.4.1 SystemC......Page 111
5.1.4.2 Esterel......Page 112
5.1.5.1 SystemC......Page 113
5.1.6.1 SystemC......Page 114
5.1.6.2 Esterel......Page 115
5.3 Feature Extensions of SystemC and Esterel......Page 117
6.1 FSM Classes......Page 119
6.1.2 Inner Classes for Transition Inputs and Transition Outputs......Page 121
6.1.3 Constructor Parameters......Page 123
6.1.6 Local Signals, Shared Variables and Channels for Lower Level FSMs and SDFGs......Page 124
6.1.6.1 Local Signal......Page 125
6.1.6.3 Channel......Page 126
6.1.8 State Refinement......Page 127
6.2.2 Instantiation of Actors......Page 129
6.2.3 Actor Connections......Page 130
6.3.3 Local Signals, Shared Variables and Channels for Top Level FSMs and SDFGs......Page 131
6.3.5 Top Level Refinement......Page 132
6.4 Simulation......Page 133
6.5.1 Base Classes......Page 134
6.5.3 FSM Communication Classes......Page 135
6.5.5 Synchronization Class......Page 136
6.6 Frequency Relay Revisited......Page 137
7.1 Background and Trends......Page 138
7.2 Architecture Framework – HETRA......Page 140
7.3 Reactive Processors as the Elements of the Heterogeneous Architecture......Page 144
7.3.1 Reactive Microprocessor – ReMIC......Page 145
7.3.1.2 SAWAIT – Signal Polling......Page 147
7.3.2 Power Aware ReMIC-PA......Page 148
7.4 Example of Heterogeneous Reactive Architecture – HiDRA......Page 150
7.4.1 An Overview of HiDRA......Page 151
7.4.2 An Implementation of HiDRA......Page 152
8.1 DFCharts Design Methodology......Page 155
8.1.1 Specification......Page 157
8.1.4 Synthesis......Page 159
8.1.5 Performance Evaluation......Page 160
8.2.2.1 Thread Entry......Page 164
8.2.2.3 Thread Exit......Page 167
8.2.4 FSM Scheduler......Page 169
8.2.5 Master Tick Handler......Page 171
8.2.6 Slave Tick Handler......Page 174
9.1 Summary and Overview......Page 180
9.2.2 Hardware Implementation......Page 182
9.2.4 Including More Expressive Dataflow Models......Page 183
9.2.7 Proof of Correctness for DFCharts Implementation......Page 184
References......Page 185
Index......Page 191