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Efficient multiplier architectures for Galois fields GF(24n )

✍ Scribed by Paar, C.; Fleischmann, P.; Roeise, P.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Multiplier architectures for GF(p) and G

✍ Savas, E.; Tenca, A.F.; Ciftcibasi, M.E.; Koc, C.K. 📂 Article 📅 2004 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 730 KB

Efficient Reconfigurable Implementation

✍ Imaña, J.L. ;Sánchez, J.M. 📂 Article 📅 2006 🏛 Springer 🌐 English ⚖ 614 KB

Digit-serial systolic multiplier for fin

✍ Guo, J.-H.; Wang, C.-L. 📂 Article 📅 1998 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 598 KB

Bit-serial systolic divider and multipli

✍ Hasan, M.A.; Bhargava, V.K. 📂 Article 📅 1992 🏛 IEEE 🌐 English ⚖ 680 KB

A universal architecture for designing e

✍ Sousa, L.; Chaves, R. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 936 KB

Efficient Montgomery-Based Semi-Systolic

✍ Zhen Wang; Shuqin Fan 📂 Article 📅 2012 🏛 IEEE 🌐 English ⚖ 545 KB