Hierarchical multi-level fault simulatio
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Daniel G. Saab; Robert B. Mueller-Thuns; David Blaauw; Joseph T. Rahmeh; Jacob A
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Article
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1990
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Springer US
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English
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This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation drastically, thus allowing the simulation of circuits that are too large to simulate a