Within control there is an ever-increasing demand for more and more computation to be performed in less and less time. Not only are applications faster, but more complex algorithms are being used to control them, and recently non-linear control algorithms are becoming more commonplace. However, if single processors are used, there is a limitation to the amount of computation possible even with modern microprocessor advances. To achieve greater speed-up, parallel hardware must be used. This will be in the form of either application-specific array processors, such as FPGAs, where VLSI technology enables many simple processors to be put on one chip, which is fine-grained parallelism, or a number of parallel processors, such as the Inmos Transputer or Texas Instruments TMS320C40 (C40), connected in a parallel network, which is coarse-grained parallelism.
Some of these pieces of hardware have been available for some time now and a number of successful implementations have been generated. However, many of these implementations have been arrived at in a rather ad hoc manner and there is still much work to be done on developing generic methods for generating parallel algorithms from first principles rather than simply implementing sequential algorithms on parallel architectures.
In the computer science literature there are many papers describing how to map algorithms onto parallel hardware. Their approach is that given a parallel computing platform, how could one map any algorithm onto it. The approach stems from a general computing perspective. Alternatively, within the digital signal-processing community the approach has been to develop application-specific hardware implementing relatively simple algorithms for very high data rates.
However, within control the algorithms are more complex than those used in DSP, although in many cases they are closely related, and the data rates are much slower, but the requirement is still for an application-specific architecture: a controller is required, not a general computing platform running a particular control programme. To meet the needs of the control community, a separate area of research has been developing: parallel processing for control.
In this special issue we hope to present a number of different ideas which will illustrate the problems and solutions that this area of research is addressing. There are five papers which illustrate a number of different techniques and perspectives.
In Reference 1 the authors seek to provide a clear description of the computational processes and associated data flow for the block-regularized parameter estimator, using hierarchical signal flow graphs (HSFGs). It describes and develops, and in some ways simplifies, some well-known techniques for devising parallel algorithms from algebraic descriptions of matrix algorithms. The