Digital system design with VHDL

✍ Scribed by Zwoliński, Mark

• Publisher: Pearson; Prentice-Hall
• Year: 2004;2010
• Tongue: English
• Leaves: 385
• Edition: 2. ed., Nachdr.
• Category: Library

✦ Synopsis

Since the publication of the first edition, a new version of the VHDL standard has been agreed and analogue extensions to the language have also been adopted. The second edition of Digital System Design with VHDL includes additions in two important areas; sections on writing testbenches have been added to relevant chapters, and the addition of a new chapter on VHDL-AMS and mixed-signal modeling. The unique approach will be appreciated by undergraduates in Electronic Engineering and Computer Engineering in all years of their courses and by students undertaking postgraduate study. There is also a proven need from industry for graduates with knowledge of VHDL and the associated design tools and this book will be an asset to engineers who wish to continue their studies.

✦ Table of Contents

Cover......Page 1
Digital System Design with VHDL......Page 2
Contents......Page 6
Preface......Page 10
Modern digital design......Page 16
CMOS technology......Page 20
Programmable logic......Page 25
Electrical properties......Page 29
Exercises......Page 33
Boolean algebra......Page 34
Combinational logic design......Page 37
Timing......Page 45
Number codes......Page 47
Exercises......Page 51
Entities and architectures......Page 53
Identifiers, spaces and comments......Page 55
Netlists......Page 56
Signal assignments......Page 59
Generics......Page 60
Constant and open ports......Page 62
Configurations......Page 63
Exercises......Page 66
Three-state buffers......Page 68
Decoders......Page 73
Multiplexers......Page 79
Priority encoder......Page 81
Adders......Page 84
Parity checker......Page 87
Testbenches for combinational blocks......Page 90
Exercises......Page 93
Synchronous sequential systems......Page 95
Models of synchronous sequential systems......Page 96
Algorithmic state machines......Page 100
Synthesis from ASM charts......Page 104
State machines in VHDL......Page 114
VHDL testbenches for state machines......Page 124
Summary......Page 126
Exercises......Page 127
Latches......Page 130
Flip-flops......Page 134
JK and T flip-flops......Page 143
Registers and shift registers......Page 147
Counters......Page 150
Memory......Page 158
Sequential multiplier......Page 162
Testbenches for sequential building blocks......Page 165
Summary......Page 168
Exercises......Page 169
Linked state machines......Page 171
Datapath/controller partitioning......Page 175
Instructions......Page 177
A simple microprocessor......Page 178
VHDL model of a simple microprocessor......Page 182
Summary......Page 191
Exercises......Page 192
Event-driven simulation......Page 193
Simulation of VHDL models......Page 197
Simulation modelling issues......Page 200
File operations......Page 201
Exercises......Page 203
VHDL synthesis......Page 205
RTL synthesis......Page 206
Constraints......Page 218
Synthesis for FPGAs......Page 221
Behavioural synthesis......Page 224
Verifying synthesis results......Page 231
Exercises......Page 233
The need for testing......Page 236
Fault models......Page 237
Fault-oriented test pattern generation......Page 239
Fault simulation......Page 246
Fault simulation in VHDL......Page 250
Summary......Page 259
Exercises......Page 260
Design for testability......Page 263
Structured design for test......Page 264
Built-in self-test......Page 267
Boundary scan (IEEE 1149.1)......Page 275
Exercises......Page 283
Asynchronous circuits......Page 286
Analysis of asynchronous circuits......Page 289
Design of asynchronous sequential circuits......Page 293
Asynchronous state machines......Page 301
Setup and hold times and metastability......Page 305
Summary......Page 312
Exercises......Page 313
Interfacing with the analogue world......Page 316
Digital to analogue converters......Page 317
Analogue to digital converters......Page 318
VHDL-AMS......Page 321
Phased-locked loops......Page 330
VHDL-AMS simulators......Page 334
Exercises......Page 336
Appendix A VHDL standards......Page 337
Appendix B Verilog......Page 342
Appendix C Shared variable packages......Page 348
Bibliography......Page 354
Answers to selected exercises......Page 356
Index......Page 378