Digital Logic Circuits

✍ Scribed by Dr. P. Kannan; Mrs. M. Saraswathi; Mr. C. Rameshkumar

• Publisher: Sree kamalamani Publications private limited
• Tongue: English
• Leaves: 809
• Category: Library

✦ Synopsis

PREFACE OF THE BOOK This book is extensively designed for the third semester EEE/EIE students as per Anna university syllabus R-2013. The following chapters constitute the following units Chapter 1, 9 covers :-Unit 1Chapter 2 and 3 covers :-Unit 2Chapter 4 and 5 covers :-Unit 3Chapter 6 and 7 covers :- Unit 4Chapter 8 VHDL :-Unit 5 CHAPTER 1: Introduces the Number System, binary arithmetic and codes. CHAPTER 2: Deals with Boolean algebra, simplification using Boolean theorems, K-map method , Quine McCluskey method, logic gates, implementation of switching function using basic Logical Gates and Universal Gates. CHAPTER 3: Describes the combinational circuits like Adder, Subtractor, Multiplier, Divider, magnitude comparator, encoder, decoder, code converters, Multiplexer and Demultiplexer. CHAPTER 4: Describes with Latches, Flip-Flops, Registers and Counters CHAPTER 5: Concentrates on the Analysis as well as design of synchronous sequential circuits, Design of synchronous counters, sequence generator and Sequence detector CHAPTER 6: Concentrates the Design as well as Analysis of Fundamental Mode circuits, Pulse mode Circuits, Hazard Free Circuits, ASM Chart and Design of Asynchronous counters. CHAPTER 7: Discussion on memory devices which includes ROM, RAM, PLA, PAL, Sequential logic devices and ASIC. CHAPTER 8: The chapter concentrates on the design, fundamental building blocks, Data types, operates, subprograms, packagaes, compilation process used for VHDL. It discusses on Finite state machine as an important tool for designing logic level state machines. The chapter also discusses register transform level designing and test benches usage in stimulation of the state logic machines CHAPTER 9: Concentrate on the comparison, operation and characteristics of RTL, DTL, TTL, ECL and MOS families. We have taken enough care to present the definitions and statements of basic laws and theorems, problems with simple steps to make the students familiar with the fundamentals of Digital Design.

✦ Table of Contents

TABLE OF CONTENTS
CHP 1-NUMBER SYSTEMAND CODES1.11.2
1.2.21.2.3
1.2.4
1.3
1.3.11.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.21.3.2.1
1.3.2.2
1.3.31.3.3.1
1.3.3.2
1.3.3.41.3.3.5
1.3.3.6
1.4
1.4.11.4.1.11.4.1.2
1.4.21.4.2.11.4.2.2
1.5
1.5.1.2
1.5.21.5.2.1
1.5.2.2
1.5.31.5.3.1
1.5.3.2
1.5.41.5.4.1
1.5.4.2
1.6
1.6.1
1.6.2
1.71.7.1
1.7.1.11.7.1.2
1.7.2.1
1.7.1.2.2
1.7.1.2.3
1.7.21.7.2.1
1.7.2.1.1
1.7.2.2
1.7.2.2.1
1.7.2.2.2
1.7.3
1.7.41.7.51.7.6
1.7.6.1
1.7.6.2
1.7.7
1.7.8
Solved Two Marks Questions
Review Questions
CHP2- MINIMIZATIONTECHNIQUES ANDLOGIC GATES2.1
2.2
2.3
2.3.1
2.3.32.3.3.12.3.3.2
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.5
2.5.12.5.2
2.5.32.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
2.6
2.72.7.1
2.7.2
2.82.8.1
2.8.2
2.92.9.1
2.9.2
2.9.3
2.9.3.1
2.9.3.2
2.9.4
2.9.4.1
2.9.4.2
Solved Two Marks Questions
Review Questions
CHP3 - COMBINATIONAL LOGIC CIRCUITS
3.13.2
3.3
3.43.4.1
3.4.2
3.53.5.1
3.5.2
3.63.6.1
3.6.2
3.6.3
3.6.4
3.7
3.83.8.1
3.8.2
3.9
3.10
3.113.11.1
3.11.2
3.11.3
3.12
3.133.13.1
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.8
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.15
Solved Two Marks Questions
Review Questions
CHP 4 - SEQUENTIAL CIRCUITS4.1
4.24.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.3.14.3.3.2
4.3.4
4.4
4.5
4.5.14.5.2
4.5.34.5.44.5.54.5.6
4.64.6.1
4.6.2
4.6.3
4.6.44.6.5
4.6.6
4.6.7
4.74.7.14.7.1.1
4.7.1.2
4.7.1.34.7.1.4
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.84.8.14.8.2
4.8.34.8.3.1
4.8.3.2
4.8.3.3
4.8.3.4
4.8.3.5
4.8.3.6
4.8.3.7
4.8.4
4.9
4.10
4.11
SOLVED TWO MARKS QUESTIONS
REVIEW QUESTIONS
CHP 5 -SYNCHRONOUS SEQUENTIAL CIRCUITS5.1
5.2
5.3
5.3.2
5.4
5.5
5.6
5.7
Solved Two Marks Questions
Review Questions
CHP 6 - ASYNCHRONOUS SEQUENTIAL CIRCUITS6.16.2
6.3
6.3.1
6.3.2
6.4
6.4.16.4.2
6.4.3
6.4.46.4.56.4.6
6.56.5.1
6.5.2
6.5.2.16.5.2.2
6.5.2.2.1
6.5.36.5.3.1
6.5.3.1.1
6.5.3.1.2
6.5.3.2
6.6
6.7
6.8
6.96.9.16.9.1.1
6.9.1.26.9.1.3
6.9.2
Solved Two Marks Questions
Review Questions
CHP 7 - MEMORY DEVICES7.1
7.2
7.2.17.2.2
7.37.4
7.4.17.4.1.17.4.1.2
7.4.1.37.4.1.47.4.1.5
7.5
7.5.1
7.5.2
7.67.6.1
7.6.2
7.77.7.1
7.7.2
7.7.3
7.87.97.10
7.117.11.1
7.11.27.12
7.12.1
7.12.2
7.13
7.13.1
7.13.2
7.13.3
7.147.14.1
7.14.2
7.14.3
7.15
7.15.17.15.27.15.2.17.15.2.2
Solved Two Marks Questions
REVIEW QUESTIONS
CHP 8 -VHDL8.18.2
8.2.18.2.28.2.38.2.48.2.5
8.2.68.3
8.3.1
8.3.2
8.3.3
8.3.3.1
8.3.3.2
8.3.3.38.3.3.4
8.3.3.5
8.3.3.6
8.48.4.18.4.28.4.38.4.3.1
8.4.3.28.4.3.38.4.3.4
8.4.48.4.4.1
8.58.5.18.5.28.5.38.5.4
8.5.58.5.68.68.6.1
8.6.28.6.38.6.4
8.78.7.18.7.28.88.8.1
8.8.28.98.9.1
8.10
8.11
Solved Two Marks Questions
Review Questions
CHP 9 - DIGITAL LOGIC FAMILIES9.1
9.29.2.1
9.2.2
9.39.3.1
9.3.2
9.3.39.3.4
9.3.5
9.49.4.1
9.4.2
9.5
9.6
9.7
9.7.1
9.7.2
9.7.39.7.3.1
9.7.3.2
9.8
9.9
9.10
9.10.1
9.10.2
9.10.3
9.119.11.1
9.11.2
9.11.3
9.11.4
9.11.5
9.129.12.19.12.29.12.39.12.4
9.12.59.12.6
9.139.14
Solved Two Marks Questions
Review Questions