Content: Preface ix Chapter 1. Latch and Flip-Flop 1 1.1. Introduction 1 1.2. General overview 1 1.2.1. SR latch 6 1.2.2. S R latch 9 1.2.3. Application: switch debouncing 11 1.3. Gated SR latch 11 1.3.1. Implementation based on an SR latch 12 1.3.2. Implementation based on an S R latch 14 1.4. Gated D latch 15 1.5. Basic JK flip-flop 16 1.6. T flip-flop 18 1.7. Master-slave and edge-triggered flip-flop 20 1.7.1. Master-slave flip-flop 20 1.7.2. Edge-triggered flip-flop 24 1.8. Flip-flops with asynchronous inputs 30 1.9. Operational characteristics of flip-flops 33 1.10. Exercises 34 1.11. Solutions 39 Chapter 2. Binary Counters 51 2.1. Introduction 51 2.2. Modulo 4 counter 52 2.3. Modulo 8 counter 53 2.4. Modulo 16 counter 55 2.4.1. Modulo 10 counter 57 2.5. Counter with parallel load 60 2.6. Down counter 62 2.7. Synchronous reversible counter 64 2.8. Decoding a down counter 65 2.9. Exercises 66 2.10. Solutions 73 Chapter 3. Shift Register 85 3.1. Introduction 85 3.2. Serial-in shift register 85 3.3. Parallel-in shift register 85 3.4. Bidirectional shift register 88 3.5. Register file 90 3.6. Shift register based counter 91 3.6.1. Ring counter 92 3.6.2. Johnson counter 93 3.6.3. Linear feedback counter 94 3.7. Exercises 101 3.8. Solutions 107 Chapter 4. Arithmetic and Logic Circuits 117 4.1. Introduction 117 4.2. Adder 117 4.2.1. Half adder 117 4.2.2. Full adder 119 4.2.3. Ripple-carry adder 120 4.2.4. Carry-lookahead adder 122 4.2.5. Carry-select adder 124 4.2.6. Carry-skip adder 125 4.3. Comparator 127 4.4. Arithmetic and logic unit 129 4.5. Multiplier 136 4.5.1. Multiplier of 2-bit unsigned numbers 136 4.5.2. Multiplier of 4-bit unsigned numbers 137 4.5.3. Multiplier for signed numbers 138 4.6. Divider 143 4.7. Exercises 149 4.8. Solutions 158 Chapter 5. Digital Integrated Circuit Technology 177 5.1. Introduction 177 5.2. Characteristics of the technologies 177 5.2.1. Supply voltage 177 5.2.2. Logic levels 178 5.2.3. Immunity to noise 178 5.2.4. Propagation delay 179 5.2.5. Electric power consumption 179 5.2.6. Fan-out or load factor 179 5.3. TTL logic family 180 5.3.1. Bipolar junction transistor 180 5.3.2. TTL NAND gate 181 5.3.3. Integrated TTL circuit 182 5.4. CMOS logic family 183 5.4.1. MOSFET transistor 183 5.4.2. CMOS logic gates 184 5.5. Open drain logic gates 185 5.5.1. Three-state buffer 187 5.5.2. CMOS integrated circuit 188 5.6. Other logic families 189 5.7. Interfacing circuits of different technologies 189 5.8. Exercises 190 5.9. Solutions 193 Chapter 6. Semiconductor Memory 195 6.1. Introduction 195 6.2. Memory organization 195 6.3. Operation of a memory 197 6.4. Types of memory 199 6.4.1. Non-volatile memory 199 6.4.2. Volatile memories 202 6.4.3. Characteristics of the different memory types 207 6.5. Applications 207 6.5.1. Memory organization 208 6.5.2. Applications 209 6.6. Other types of memory 218 6.6.1. Ferromagnetic RAM 220 6.6.2. Content-addressable memory 222 6.6.3. Sequential access memory 223 6.7. Exercises 226 6.8. Solutions 230 Chapter 7. Programmable Logic Circuits 245 7.1. General overview 245 7.2. Programmable logic device 246 7.3. Applications 255 7.3.1. Implementation of logic functions 255 7.3.2. Two-bit adder 257 7.3.3. Binary-to-BCD and BCD-to-binary converters 263 7.4. Programmable logic circuits (CPLD and FPGA) 263 7.4.1. Principle and technology 264 7.4.2. CPLD 268 7.4.3. FPGA 270 7.5. References 274 7.6. Exercises 275 7.7. Solutions 284 Appendix 307 Bibliography 309 Index 311