โ Scribed by David J. Lilja, Sachin S. Sapatnekar
No coin nor oath required. For personal study only.
This book explains how to specify, design, and test a complete digital system using Verilog.
Cover......Page 1
Half-title......Page 3
Title......Page 5
Copyright......Page 6
Contents......Page 7
Preface......Page 9
Suggestions for using this text......Page 10
Acknowledgements......Page 11
1.1 Hierarchical design flow......Page 12
1.2 Designing hardware with software......Page 15
1.3 Summary......Page 17
2.1 My Veri first description......Page 18
2.2.1 Modules and ports......Page 20
2.2.2 Nets and registers......Page 21
2.2.3 Vectors and arrays......Page 22
2.2.4 Constants......Page 23
2.2.5 Number representation......Page 24
2.2.6 Operators......Page 25
2.3 Behavioral and structural models......Page 27
2.3.1 An example of a finite state machine......Page 28
2.3.2 Behavioral modeling......Page 29
Timing controls......Page 32
Blocking and nonblocking assignments......Page 33
Loops......Page 35
2.3.4 Structural description......Page 36
2.4 Functions and tasks......Page 39
2.5 Summary......Page 41
Further reading......Page 42
3.1 Instruction set design......Page 43
Specifying operands......Page 46
Choosing specific instructions......Page 47
Arithmetic overflow......Page 48
Arithmetic carry out......Page 49
3.2.3 Control instructions......Page 50
Condition codes......Page 52
Setting the condition codes......Page 53
Conditional branching......Page 54
Load-store and memory-to-memory architectures......Page 56
The VeSPA load-store instructions......Page 57
3.2.5 Miscellaneous instructions......Page 58
3.3.1 The instruction format......Page 59
Arithmetic and logical instructions......Page 62
Control instructions......Page 63
Data transfer instructions......Page 65
Further reading......Page 67
4 Algorithmic behavioral modeling......Page 69
4.2.1 Parameters......Page 70
4.2.2 Register declarations......Page 71
4.2.3 Instruction field and opcode definitions......Page 73
4.3 Fetch-execute loop......Page 75
4.4 Fetch task......Page 79
4.4.1 Memory interface......Page 80
4.5 Execute task......Page 82
4.6 Condition code tasks......Page 88
4.7 Tracing instruction execution......Page 90
4.8 Summary......Page 92
5.1 Why assembly language?......Page 93
5.2 The assembly process......Page 94
Label Operation Operands Comment......Page 95
5.2.2 Two-pass assembler......Page 96
5.3.1 VASM syntax and assembler commands......Page 99
5.3.2 Pass 1 โ lexical analysis and parsing......Page 101
5.3.3 Pass 2 โ machine code generation......Page 102
5.5 Summary......Page 103
6.1 Instruction partitioning for pipelining......Page 105
6.2 Pipeline performance......Page 107
6.3 Dependences and hazards......Page 108
Control dependences......Page 109
6.3.2 Pipeline hazards......Page 110
Branch hazards......Page 111
Data hazards......Page 112
Structural hazards......Page 113
6.4 Dealing with pipeline hazards......Page 114
Further reading......Page 115
7.1 Pipelining VeSPA......Page 116
7.2 The hazard detection unit......Page 117
7.3 Overview of the pipeline structure......Page 119
7.4.1 The instruction fetch (IF) stage......Page 120
7.4.2 The instruction decode (ID) stage......Page 122
7.4.3 The execute (EX) stage......Page 124
7.4.4 The memory access (MEM) and write back (WB) stages......Page 125
7.5 Timing considerations......Page 126
Further reading......Page 128
8.1 Component-level test benches......Page 129
8.1.1 Using manually generated test vectors......Page 130
8.1.2 Using automatically generated test vectors......Page 133
8.1.3 Constrained pseudorandom test vectors......Page 136
8.2 System-level self-testing......Page 138
8.2.1 Initial steps......Page 139
8.2.2 Program structure......Page 140
8.3 Formal verification......Page 141
Further reading......Page 142
A.1 Notational conventions......Page 143
A.3 The instruction specifications......Page 144
Description......Page 145
Description......Page 146
Instruction encoding......Page 147
Instruction encoding......Page 148
Detailed operation......Page 149
Assembly code notation......Page 150
Assembly code notation......Page 151
Assembly code examples......Page 152
Assembly code examples......Page 153
Assembly code notation......Page 154
Assembly code examples......Page 155
Assembly code examples......Page 156
Assembly code examples......Page 157
B.1 Notational conventions......Page 158
B.2 Assembler directives......Page 159
B.4 Modifying the assembler......Page 160
B.4.1 Lexical analysis and parsing modifications......Page 161
Further reading......Page 163
Index......Page 164
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