✦ LIBER ✦

Design, performance, and extensions of the RAM-DFE architecture

✍ Scribed by Bednarz, P.S.; Lin, S.C.; Modlin, C.S.; Cioffi, J.M.

Book ID: 114548298
Publisher: IEEE
Year: 1995
Tongue: English
Weight: 601 KB
Volume: 31
Category: Article
ISSN: 0018-9464
DOI: 10.1109/20.364806

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Performance, Power, and Reliability Trad

Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement

✍ Hai Li; Xiaobin Wang; Zhong-Liang Ong; Weng-Fai Wong; Yaojun Zhang; Peiyuan Wang 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 545 KB

Design, Architecture and Performance Eva

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

✍ N. Sklavos; P. Kitsos; K. Papadopoulos; O. Koufopavlou 📂 Article 📅 2006 🏛 Springer US 🌐 English ⚖ 440 KB

Design and performance evaluation of rea

Design and performance evaluation of real-time communication architectures

✍ Elnakhal, A.E.; Rzehak, H. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 774 KB

Iterative design and detection of a DFE

Iterative design and detection of a DFE in the frequency domain

✍ Benvenuto, N.; Tomasin, S. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 390 KB

The Art of Hardware Architecture || Desi

The Art of Hardware Architecture || Design Guidelines for EMC Performance

✍ Arora, Mohit 📂 Article 📅 2011 🏛 Springer New York 🌐 English ⚖ 309 KB

This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and

Integrating computer architectures into

Integrating computer architectures into the design of high-performance controllers

✍ Jacklin, S.; Leyland, J.; Warmbrodt, W. 📂 Article 📅 1986 🏛 IEEE 🌐 English ⚖ 752 KB