Design of a tunable multi-band differential LC VCO using 0.35 μm SiGe BiCMOS technology for multi-standard wireless communication systems

✍ Scribed by Ahmet Kemal Bakkaloglu; Arzu Ergintav; Emre Ozeren; Ibrahim Tekin; Yasar Gurbuz

• Publisher: Elsevier Science
• Year: 2009
• Tongue: English
• Weight: 591 KB
• Volume: 40
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/j.mejo.2008.10.004

✦ Synopsis

In this paper, an integrated 2.2-5.7 GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2. GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and À6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as À37.21 and À47.6 dBm, respectively. The phase noise between À110.45 and À122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between À176.48 and À181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between À6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm 2 on Si substrate, including DC, digital and RF pads.