✦ LIBER ✦

Design of a Sub-1.5 V, 20 MHz, 0.1% MOS Current-Mode Sample-and-Hold Circuit

✍ Scribed by Yasuhiro Sugimoto; Masahiro Sekiya

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 1.5-V 50-MHz pseudodifferential CMOS s

✍ Tsung-Sum Lee, ; Chi-Chang Lu 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 572 KB

A 200 MHz pipelined multiplier using 1.5

✍ Hanyu, T.; Kameyama, M. 📂 Article 📅 1995 🏛 IEEE 🌐 English ⚖ 858 KB

Analysis and Design of a Low-Voltage, Lo

✍ Sawigun, C.; Serdijn, W.A. 📂 Article 📅 2011 🏛 Institute of Electrical and Electronics Engineers 🌐 English ⚖ 637 KB

A 1.5-V current-mode CMOS sample-and-hol

✍ Sugimoto, Y. 📂 Article 📅 2001 🏛 IEEE 🌐 English ⚖ 109 KB

[IEEE 2010 IEEE International Symposium

✍ Sawigun, Chutham; Serdijn, Wouter A. 📂 Article 📅 2010 🏛 IEEE ⚖ 258 KB

[IEEE 2005 European Conference on Circui

✍ Koike, T.; Hyogo, A.; Sekine, K. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 249 KB