Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers
✍ Scribed by Nobuhiro Tomabechi; Teruki Ito
- Publisher
- John Wiley and Sons
- Year
- 2002
- Tongue
- English
- Weight
- 264 KB
- Volume
- 33
- Category
- Article
- ISSN
- 0882-1666
- DOI
- 10.1002/scj.1122
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✦ Synopsis
Abstract
The RSA cryptosystem plays an important role in ensuring the security of network communications, although it has the drawback that much time is required for encryption/decryption. This paper presents a high‐speed RSA encryption processor employing highly parallel operation based as much as possible in the hardware technology as follows: (1) All of the arithmetic circuits required for encryption/decryption are implemented in the form of redundant binary numbers. (2) Residue calculation is performed by table look‐up in a hardware table built in the processor. The table look‐up is done in the form of redundant binary numbers. The operation speed of the proposed processor is found to be 60 times that of usual processors when the key length N is 1024 bits. Also, the order of the encryption time of the processor is O(N__log__N). The chip size of the processor is estimated as (4.3 × 10^5^ λ) × (5.63 × 10^5^ λ), where λ denotes the standard size in the layout design. The chip size becomes 10.9 cm × 14.1 cm when the 0.5−µm rule, which corresponds to λ = 0.25 µm, is used, hence the processor can be integrated on an 8‐inch wafer. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(5): 1–10, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1122