✦ LIBER ✦
Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops
✍ Scribed by Jinn-Shyan Wang; Po-Hui Yang; Duo Sheng
- Book ID
- 119775557
- Publisher
- IEEE
- Year
- 2000
- Tongue
- English
- Weight
- 404 KB
- Volume
- 35
- Category
- Article
- ISSN
- 0018-9200
- DOI
- 10.1109/4.839918
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