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Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application

✍ Scribed by Tran, X.T.; Thonnart, Y.; Durupt, J.; Beroulle, V.; Robach, C.

Book ID: 117809852
Publisher: The Institution of Engineering and Technology
Year: 2009
Tongue: English
Weight: 847 KB
Volume: 3
Category: Article
ISSN: 1751-8601
DOI: 10.1049/iet-cdt.2008.0072

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