Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

✍ Scribed by Brandon Noia, Krishnendu Chakrabarty (auth.)

Publisher: Springer International Publishing
Year: 2014
Tongue: English
Leaves: 260
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

✦ Table of Contents

Front Matter....Pages i-xviii
Introduction....Pages 1-10
Wafer Stacking and 3D Memory Test....Pages 11-54
Built-In Self-Test for TSVs....Pages 55-79
Pre-bond TSV Test Through TSV Probing....Pages 81-113
Pre-bond Scan Test Through TSV Probing....Pages 115-135
Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths....Pages 137-158
Post-Bond Test Wrappers and Emerging Test Standards....Pages 159-180
Test-Architecture Optimization and Test Scheduling....Pages 181-237
Conclusions....Pages 239-240
Back Matter....Pages 241-245

✦ Subjects

Circuits and Systems; Processor Architectures; Semiconductors

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