Design criteria for low noise front-end electronics in the 0.13 μm CMOS generation

✍ Scribed by Valerio Re; Massimo Manghisoni; Lodovico Ratti; Valeria Speziali; Gianluca Traversi

• Publisher: Elsevier Science
• Year: 2006
• Tongue: English
• Weight: 303 KB
• Volume: 568
• Category: Article
• ISSN: 0168-9002
• DOI: 10.1016/j.nima.2006.06.003

✦ Synopsis

The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13 mm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments (SLHC, ILC, Super B-Factory).