We consider an ATh4 switch consisting of a number of output-buffered ATM switch elements operating in parallel. Such an architecture may lead to uneven distribution of cells over the parallel switch element buffers, if no modifications to the design is made. 'With this motivation, we propose a thres
โฆ LIBER โฆ
Design and performance analysis of a practical load-balanced switch
โ Scribed by Yanming Shen; Panwar, S.S.; Chao, H.J.
- Book ID
- 114610931
- Publisher
- IEEE
- Year
- 2009
- Tongue
- English
- Weight
- 488 KB
- Volume
- 57
- Category
- Article
- ISSN
- 0090-6778
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