Design and fault diagnosis of cellular arrays realizing multiple-valued logic functions
✍ Scribed by Naotake Kamiura; Yutaka Hata; Kazuharu Yamato
- Publisher
- John Wiley and Sons
- Year
- 1994
- Tongue
- English
- Weight
- 938 KB
- Volume
- 25
- Category
- Article
- ISSN
- 0882-1666
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✦ Synopsis
Abstract
An efficient fault diagnostic method should be developed to reduce the turnaround time and the cost for developing binary LSI's. For the multiple‐valued logic system that has been expected in the post‐binary electronics, research on the fault diagnosis for the logic circuit will be essential.
This paper discusses the design and the fault diagnosis in multiple‐valued cellular arrays. First, the single‐level array, two‐level array, three‐level array, and n‐level array realizing k‐valued n‐variable logic functions are introduced. It is clarified that the two‐level array is the most suitable structure solving both problems of the number of cells and the fault location.
Next, further investigation is made for the fault diagnosis. The stuck‐at faults, the open fault, and the AND bridging fault are treated under the assumption that the single fault occurs in the array. In the authors' fault diagnostic method, the test inputs can easily be generated from the control inputs that specify the switches of cells. Moreover, the comparison with other testing methods for cellular arrays shows that our method reduces the order of steps for generating all test inputs.