Defect- and fault-tolerant static ram module designs based on parity checking and automatic testing
✍ Scribed by Nobuo Tsuda
- Book ID
- 104591555
- Publisher
- John Wiley and Sons
- Year
- 1993
- Tongue
- English
- Weight
- 721 KB
- Volume
- 24
- Category
- Article
- ISSN
- 0882-1666
No coin nor oath required. For personal study only.
✦ Synopsis
Abstract
Advanced redundancy configurations are presented for static RAM modules. These extend the word duplication and selection by horizontal parity checking (WDSH) and error correction by horizontal and vertical parity checking (ECHV) configurations to enhance yields of wafer‐scale integrated circuits. They use automatic spare block replacements for bit‐lines and word‐lines, word selection by access error checking, pair unit replacement, and two‐level hierarchical redundancy.
A simulation using a 1.5‐μm, 128 k‐bit CMOS static RAM module suggests that defect‐ and fault‐tolerance capability is improved nine or 17 times over the basic redundancy configurations. These values are four or six times that achieved by conventional triple‐modular redundancy (TMR).