Current Trends in Hardware Verification and Automated Theorem Proving

✍ Scribed by Avra Cohn (auth.), Graham Birtwistle, P. A. Subrahmanyam (eds.)

• Publisher: Springer-Verlag New York
• Year: 1989
• Tongue: English
• Leaves: 498
• Edition: 1
• Category: Library

✦ Synopsis

This report describes the partially completed correctness proof of the Viper 'block model'. Viper [7,8,9,11,23] is a microprocessor designed by W. J. Cullyer, C. Pygott and J. Kershaw at the Royal Signals and Radar Establishment in Malvern, England, (henceforth 'RSRE') for use in safety-critical applications such as civil aviation and nuclear power plant control. It is currently finding uses in areas such as the de­ ployment of weapons from tactical aircraft. To support safety-critical applications, Viper has a particulary simple design about which it is relatively easy to reason using current techniques and models. The designers, who deserve much credit for the promotion of formal methods, intended from the start that Viper be formally verified. Their idea was to model Viper in a sequence of decreasingly abstract levels, each of which concentrated on some aspect ofthe design, such as the flow ofcontrol, the processingofinstructions, and so on. That is, each model would be a specification of the next (less abstract) model, and an implementation of the previous model (if any). The verification effort would then be simplified by being structured according to the sequence of abstraction levels. These models (or levels) of description were characterized by the design team. The first two levels, and part of the third, were written by them in a logical language amenable to reasoning and proof.

✦ Table of Contents

Front Matter....Pages i-x
Correctness Properties of the Viper Block Model: The Second Level....Pages 1-91
Formal Verification of the Sobel Image Processing Chip....Pages 92-127
Specification-driven Design of Custom Hardware in HOP....Pages 128-170
Formal Verification of a Microprocessor Using Equational Techniques....Pages 171-218
OBJ as a Theorem Prover with Applications to Hardware Verification....Pages 219-267
Formal Verification in m-EVES....Pages 268-302
The Interactive Proof Editor An Experiment in Interactive Theorem Proving....Pages 303-322
An Overview of the Edinburgh Logical Framework....Pages 323-340
Automating Recursive Type Definitions in Higher Order Logic....Pages 341-386
Mechanizing Programming Logics in Higher Order Logic....Pages 387-439
Automated Theorem Proving for Analysis and Synthesis of Computations....Pages 440-464
What Do Computer Architects Design Anyway?....Pages 465-479
Back Matter....Pages 481-489

✦ Subjects

Computer System Implementation;Electronics and Microelectronics, Instrumentation