Co-Verification of Hardware and Software for ARM SoC Design
β Scribed by Jason Andrews
- Book ID
- 127444373
- Publisher
- Elsevier
- Year
- 2005
- Tongue
- English
- Weight
- 3 MB
- Series
- Embedded technology series
- Edition
- 5
- Category
- Library
- City
- Amsterdam; Boston
- ISBN
- 0750677309
No coin nor oath required. For personal study only.
β¦ Synopsis
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing.This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.The ONLY book on verification for systems-on-a-chip (SoC) on the marketWill save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes*Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easilyuse it in their own designs
π SIMILAR VOLUMES
## Abstract In this paper we present a methodology for formal verification of hardware/software coβdesigns which are represented in RTL/program codes. Two methodologies are proposed. One is for property checking of the aboveβmentioned coβdesigns, and the other is for equivalence checking between de