CMOS Processors and Memories (Analog Circuits and Signal Processing)

✍ Scribed by Krzysztof Iniewski (editor)

• Publisher: Springer
• Year: 2010
• Tongue: English
• Leaves: 381
• Category: Library

✦ Synopsis

CMOS Processors and Memories addresses the-state-of-the-art in integrated circuit design in the context of emerging computing systems. New design opportunities in memories and processor are discussed. Emerging materials that can take system performance beyond standard CMOS, like carbon nanotubes, graphene, ferroelectrics and tunnel junctions are explored.

CMOS Processors and Memories is divided into two parts: processors and memories. In the first part we start with high performance, low power processor design, followed by a chapter on multi-core processing. They both represent state-of-the-art concepts in current computing industry. The third chapter deals with asynchronous design that still carries lots of promise for future computing needs. At the end we present a “hardware design space exploration” methodology for implementing and analyzing the hardware for the Bayesian inference framework. This particular methodology involves: analyzing the computational cost and exploring candidate hardware components, proposing various custom architectures using both traditional CMOS and hybrid nanotechnology CMOL. The first part concludes with hybrid CMOS-Nano architectures.

The second, memory part covers state-of-the-art SRAM, DRAM, and flash memories as well as emerging device concepts. Semiconductor memory is a good example of the full custom design that applies various analog and logic circuits to utilize the memory cell’s device physics. Critical physical effects that include tunneling, hot electron injection, charge trapping (Flash memory) are discussed in detail. Emerging memories like FRAM, PRAM and ReRAM that depend on magnetization, electron spin alignment, ferroelectric effect, built-in potential well, quantum effects, and thermal melting are also described.

CMOS Processors and Memories is a must for anyone serious about circuit design for future computing technologies. The book is written by top notch international experts in industry and academia. It can be used in graduate course curriculum.

✦ Table of Contents

CMOS Processorsand Memories
Contents
Part I:Processors
Chapter 1: Design of High Performance Low Power Microprocessors
1.1 Introduction
1.2 Concurrent Multi-threading (CMT)
1.3 Power and Power Management
1.3.1 Dynamic Power
1.3.1.1 Activity Factor and Switching Capacitance
1.3.1.2 Voltage (VDD) and Frequency of Operation
1.3.1.3 Crowbar Power
1.3.2 Static (Leakage) Power
1.3.2.1 Sub-threshold Leakage
1.3.2.2 Gate Leakage
1.3.2.3 Diode Leakage
1.3.2.4 Effect of VDD and Temperature on Leakage
1.3.2.5 Back Bias
1.3.3 Using VDD and Back-Bias to Optimize for Performance and Power
1.3.4 Power Management: What and How?
1.3.4.1 Dynamic Voltage and Frequency Scaling
1.3.4.2 Other Power Management Techniques
1.4 Clock Design
1.4.1 Clock Skew/Clock Uncertainty
1.4.1.1 Sources of Clock Skew/Clock Uncertainty
1.5 Memory Design
1.5.1 The 6-T Memory Cell
1.5.1.1 Important Metrics/Tests for Evaluating a 6-T Memory Cell
1.5.2 Memory Redundancy
1.5.3 The Importance of Statistical Analysis
1.6 Process Technology and Impact of Layout on Performance and Power
1.7 Conclusion
References
Chapter 2: Towards High-Performance and Energy-Efficient Multi-core Processors
2.1 Motivating Multi-core Processors
2.1.1 Challenges on Uni-core Processors
2.1.1.1 High Performance Innovations are Challenging
2.1.1.2 Power Dissipation Becomes the Key Constraint
2.1.1.3 The Gap Between Dream and Reality on Performance and Energy Efficiency
2.1.1.4 Future Fabrication Technologies Imposing New Challenges
2.1.2 Challenges on ASIC Implementations
2.1.3 Solution: Multi-core Processors
2.2 Pioneering Multiprocessor Systems and Multi-core Processors
2.2.1 Communication Model: Shared-Memory and Message Passing
2.2.2 Interconnect Topology
2.2.3 Some Design Cases
2.3 Modern Multi-core Processors
2.3.1 Design Cases of Modern Multi-core Processors
2.3.2 Distinguishing Multi-core Processors
2.4 Looking Forward to the Future of Multi-core Processors
2.4.1 There is no Universal Multi-core Processor
2.4.2 Fault-Tolerance Will Become a Key Issue in Multi-core Processors
Reference
Chapter 3: Low Power Asynchronous Circuit Design: An FFT/IFFT Processor
3.1 Introduction
3.2 Synchronization: Synchronous and Asynchronous
3.2.1 Synchronous Approach
3.2.2 Asynchronous Approach
3.2.2.1 Delay Models
3.2.2.2 Handshaking Protocols and Channels
3.2.2.3 Data Encoding
3.2.2.4 Asynchronous Pipelines
3.3 Low Power Asynchronous Micro/Macro Cells
3.3.1 Latch Adder
3.3.2 Asynchronous Carry Completion Sensing Adders
3.3.3 Multiplier
3.3.4 Memory
3.4 Low Power Asynchronous FFT/IFFT Processor
3.4.1 FFT/IFFT Algorithm
3.4.2 Benchmarked Synchronous FFT/IFFT Processor
3.4.3 Asynchronous FFT/IFFT Processor
3.4.4 Comparison of the Synchronous and Asynchronous Designs
3.5 Conclusions
References
Chapter 4: CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price
4.1 Introduction
4.2 Hardware for Computational Models
4.2.1 Hardware Virtualization Spectrum
4.2.2 Existing Hardware Implementations of George and Hawkins’ Model
4.2.3 Hardware Design Space Exploration: An Architecture Assessment Methodology
4.3 A Bayesian Memory (BM) Module
4.4 Hardware Architectures for Bayesian Memory
4.4.1 Definition of Hardware Architectures for BM
4.4.2 General Issues
4.4.2.1 Precision/Bits
4.4.2.2 Communication
4.4.2.3 Number of Parent and Child BMs, and Code Book (CB) Size
4.4.2.4 Virtualization
4.4.2.5 Hybrid Nanotechnology – CMOL
4.5 Digital CMOS and CMOL Hardware Architectures for Bayesian Memory (BM)
4.5.1 Floating-Point (FLP) Architecture
4.5.2 Logarithmic Number System (LNS) Architecture
4.5.3 Fixed-Point (FXP) Architecture
4.6 Mixed-Signal (MS) CMOS and CMOL Hardware Architectures for Bayesian Memory (BM)
4.6.1 Mixed-Signal CMOS Architecture
4.6.2 Mixed-Signal CMOL Architecture
4.7 Performance/Price Analysis and Results
4.7.1 Performance/Price Analysis
4.7.2 Performance/Price Results and Discussion
4.7.3 Scaling Estimates for BM Based Cortex-Scale System
4.8 Conclusion, Contribution and Future Work
4.9 Appendix
4.9.1 Digital FLP or LNS Architecture
4.9.1.1 Time
4.9.1.2 Area
4.9.1.3 Power
4.9.2 Digital FXP Architecture
4.9.2.1 Time
4.9.2.2 Area
4.9.2.3 Power
4.9.3 Mixed-Signal CMOS Architecture
4.9.3.1 Time
4.9.3.2 Area
4.9.3.3 Power
4.9.4 Mixed-Signal CMOL Architecture
4.9.4.1 MS CMOL Nanogrid for the SVMM
4.9.4.2 Time
4.9.4.3 Area
4.9.4.4 Power
4.9.5 Example: Use of Architecture Assessment Methodology for Associative Memory Model
References
Chapter 5: A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture
5.1 Introduction
5.2 Nanoscale Technologies and Devices
5.2.1 Nanoscale Switches and the Crossbar Array
5.2.1.1 Nanoscale Switches
Self Assembled Molecular Electronics
Phase Change Devices
Generic MRAM Device
Metal Oxide Device
5.2.1.2 Resonant Tunneling Diodes
5.2.2 Fundamental Circuits
5.2.2.1 Crossbar Array
5.2.2.2 Programmable Logic Array (PLA)
5.2.2.3 Goto Pair
5.2.3 Device Modelling
5.3 The Programmable Majority Logic Array
5.4 A CMOS-Nano PMLA Based FPGA
5.4.1 Partitioning Logic Between CMOS and Nano
5.4.1.1 All Nano PMLA Mapping
5.4.1.2 Equal Partitioning Between CMOS and Nano
5.4.2 Results and Comparisons
5.4.3 Impact: Considerations for Designing CMOS/Nano Circuits
5.5 Future Prospects (Memristors)
5.6 Summary
References
Part II:Memories
Chapter 6: Memory Systems for Nano-computer
6.1 Introduction
6.1.1 The Value of a Computer
6.1.2 The Origin of a Computer Body
6.1.3 The Birth of a Memory Device
6.1.4 The Brief on a Computer System
6.1.5 The Brief on a Memory Hierarchy
6.2 Memory Devices and Circuits
6.2.1 The Foundation of a Memory Core
6.2.2 The Foundation of a Memory Design
6.2.2.1 Analog Circuits for a Memory Device
6.2.2.2 Logic Circuits for a Memory Device
6.2.3 The Brief on the Interconnect Issues
6.3 Memory Hierarchy and Hardware Compositions
6.3.1 The Types of Memories
6.3.2 The Memory Architectures
6.3.3 The Brief on a Memory Controller
6.3.4 The Memory Hierarchy
6.3.5 The Future of the Memory Hierarchy
6.3.6 The Device-Level Innovations
6.4 Software Interfaces of Memory Devices
6.4.1 The Memory as a System Resource
6.4.2 The Software Overhead in a Memory-related Performance
6.4.3 The Future Computing System
6.4.3.1 Evolution of a Memory System
6.4.3.2 Evolution of a Storage System
6.5 The Top-down Approach: Wrap-up
6.6 Conclusion
References
Chapter 7: Flash Memory
7.1 Introduction to Flash Memory
7.1.1 Introduction
7.1.2 Semiconductor Memory
Non-Volatile Memory
7.1.3 Flash Memory
7.2 Flash Memory Architecture
7.2.1 Chip Architecture
7.2.2 Basic Operating Principles of Flash-Cell
7.2.3 Memory Array Architecture
7.2.4 Program Operation
7.2.5 Erase Operation
7.2.6 Read Operation
7.3 MLC Technology
7.3.1 Concept of MLC Technology
7.3.2 Precise Charge Placement in MLC Technology
7.3.3 Precise Charge Sensing in MLC Technology
7.4 Flash Memory Reliability
7.4.1 Endurance
7.4.2 Data Retention
7.5 Flash Memory Scaling
7.5.1 Cell Scaling Issues
7.5.2 Alternative Method for High Density
7.6 Conclusions
References
Chapter 8: CMOS-based Spin-Transfer Torque Magnetic Random Access Memory (ST–MRAM)
8.1 Introduction
8.2 CMOS-based ST–MRAM Elements
8.2.1 Background
8.2.2 Current Issues
8.3 Magnetization Dynamics in ST–MRAM Elements
8.3.1 Method of Micromagnetic Modeling
8.3.2 Spin-Polarized Current Pulse Switching of Ni80Fe20/Cu/Co Nanopillar Elements
8.3.3 Fabrication and Characterization of Prototype ST–MRAM
8.3.3.1 Fabrication of 8 × 8 Array of ST–MRAM Nanopillar Elements
8.3.3.2 Characterization of ST–MRAM Nanopillar Elements
8.4 Conclusions
References
Chapter 9: Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities
9.1 Introduction to Spin Torque Random Access Memory
9.2 Magnetization Switching Challenges as SPRAM Scales Down
9.3 SPRAM Device Characterization and System Scaling Down Requirement
9.3.1 Characterization of Spin Torque Induced Magnetization Switching
9.3.2 SPRAM System Dynamic Modeling
9.3.3 SPRAM Scale Down Requirments
9.4 Reasearch and Development Opportunities for Switching Current Reduction and Variability Control
9.4.1 Current Reduction Through Changing Magnetic Properties
9.4.2 Current Reduction Through Decreasing Damping by Changing Interfacial Tunneling Properties
9.4.3 Current Reduction Through Increasing Spin Torque Efficiency
9.4.4 Currnt Reduction Through Time and Spatial Varying Polarized Current
9.4.5 Current Reduction Through Coupled Magnetic Elements and Nonunifrom Magnetization Switching
9.4.6 Current Reduction Through Thermal Spin Torque Switching
9.4.7 Variability Control at Device Level
9.4.8 Variability Control at System Level
References
Chapter 10: High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies
10.1 Introduction
10.2 Evolution for High Performance Embedded DRAMs
10.3 Principles of High Performance Embedded DRAM Technology, Architecture, and Designs
10.3.1 Technology
10.3.2 Macro Architecture
10.3.3 Modes of Operation
10.3.3.1 Single Bank Fast Random Access Cycle Mode
10.3.3.2 Multi Bank Pipeline Mode
10.3.4 Wordline Architectures
10.3.5 Bitline Architectures
10.3.6 Sensing Schemes
10.3.7 Late Write, Early Write, and Direct Write
10.3.8 Negative Wordline Architecture
10.3.9 Concurrent Refresh Mode
10.3.10 Redundancy
10.3.11 Test Methodology
10.4 IBM Embedded DRAM Macros
10.4.1 Embedded DRAMs for ASIC
10.4.2 Embedded DRAM with Destructive Read Architecture
10.4.3 Embedded DRAM for High-performance SOI Microprocessor
10.5 High Performance Cache with Embedded DRAM Macros
10.5.1 Architecture
10.5.2 ABIST and FAR
10.5.3 Refresh Management
10.6 Future Work
10.6.1 Embedded DRAM with Floating Body Cell
10.6.2 Embedded DRAM with Gain Cell
10.6.3 Embedded DRAM with Twin Cell
10.6.4 Embedded DRAM for 3 Dimensional Integration
10.6.5 Summary
References
Chapter 11: Timing Circuit Design in High Performance DRAM
11.1 Introduction
11.1.1 Memory Interface
11.1.2 Evolution of the DRAM Interface and Timing Specifications
11.1.3 Source-Synchronous Interface and Matched Routing
11.1.4 Timing Adjust Circuitry
11.2 Clock Distribution Network
11.2.1 CML Versus CMOS
11.2.2 Clock Division and Multiphase Clocking
11.2.3 Voltage and Temperature Insensitive CDN
11.2.4 Self-adaptive Bias Generator
11.2.5 Simulation Results
11.3 Clock Synchronization Circuits
11.3.1 MDLL Clocking Architecture
11.3.2 Fast-Lock Digital DLL
11.3.3 Analog Phase Generator (APG)
11.3.4 Measurement Results
11.3.5 Other Consideration
11.4 Future Directions for Nanoscaled DRAM Interface
References
Chapter 12: Overview and Scaling Prospect of Ferroelectric Memories
12.1 Introduction
12.2 FeRAM Principle and Read/Write Mechanism
12.3 Conventional 1T/1C FeRAM and Current Memory Cell Structures
12.4 Chain FeRAM Architecture and Development History
12.5 Scaling Techniques to Reduce Bitline Capacitance
12.6 Dummy Cell Design Techniques
12.7 Cell Signal Enhancement Techniques
12.8 Reliability Issues
12.9 Future Prospect of FeRAMs – 3D Capacitor and New FeRAM
12.10 Application as Nonvolatile FeRAM Cache
12.11 Conclusions
References