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CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

✍ Scribed by Gonzalez, A.F.; Bhattacharya, M.; Kulkarni, S.; Mazumder, P.

Book ID: 119775887
Publisher: IEEE
Year: 2001
Tongue: English
Weight: 250 KB
Volume: 36
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.924855

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[IEEE Comput. Soc 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) - Portland, OR, USA (23-25 May 2000)] Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000) - Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

✍ Gonzalez, A.F.; Bhattacharya, M.; Kulkarni, S.; Mazumder, P. 📂 Article 📅 2000 🏛 IEEE Comput. Soc 🌐 English ⚖ 598 KB