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Circuits over monoids: a fault model, and a trade-off between testability and circuit delay

✍ Scribed by H.A. Farhat; J.C. Birget

Publisher: Elsevier Science
Year: 1992
Tongue: English
Weight: 297 KB
Volume: 5
Category: Article
ISSN: 0893-9659
DOI: 10.1016/0893-9659(92)90064-g

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✦ Synopsis

We introduce a new fault model for evaluation circuits and prefix circuits over a transformation monoid. For evaluation circuits we give a trade-off between the delay of the circuit and the number of test-inputs needed to detect faultiness.

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