A synthesis system based on a circuit simulator and a silicon assembler for analog neural networks to be implemented in MOS technology is presented. The system approximates on-chip training of the neural network under consideration and provides the best starting point for 'chip-in-the-loop training'
Circuit layout through an analogy with neural networks
β Scribed by D.S. Rao; L.M. Patnaik
- Publisher
- Elsevier Science
- Year
- 1992
- Tongue
- English
- Weight
- 817 KB
- Volume
- 24
- Category
- Article
- ISSN
- 0010-4485
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β¦ Synopsis
Standard-cell design methodology is an important technique in semicustom-VLSI design. It lends itself to the easy automation of the crucial layout part, and many algorithms have been proposed in recent literature for the efficient placement of standard cells. While many studies have identified the Kernighan-Lin bipartitionin9 method as bein9 superior to most others, it must be admitted that the behaviour of the method is erratic, and that it is strongly dependent on the initial partition. This paper proposes a novel algorithm for overcomin9 some of the deficiencies of the Kernighan-Lin method. The approach is based on an analogy of the placement problem with neural networks, and, by the use of some of the organizin9 principles of these nets, an attempt is made to improve the behavior of the bipartitionin9 scheme. The results have been encouraging, and the approach seems to be promisin 9 for other NP-complete problems in circuit layout.
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