Capacitated transit assignment with loading priorities
β Scribed by Younes Hamdouch; Patrice Marcotte; Sang Nguyen
- Book ID
- 106275436
- Publisher
- Springer-Verlag
- Year
- 2004
- Tongue
- English
- Weight
- 220 KB
- Volume
- 101
- Category
- Article
- ISSN
- 0025-5610
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
For maximum efficiency in a multiprocessor system the load should be shared evenly over all processors; that is, there should be no idle processors when tasks are available. The delay in a load-sharing algorithm is the larger of the maximum time that any processor can be idle before a task is assign
## Abstract A new miniature dual behavior resonator (DBR) topology with capacitors placed in series between the feed lines and the stubs is demonstrated. Design equations are derived. For a proofβofβconcept, a firstβorder prototype with a 1βGHz working frequency and 70% size reduction is realized,