Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures

✍ Scribed by Mark Wijtvliet, Henk Corporaal, Akash Kumar

• Publisher: Springer
• Year: 2021
• Tongue: English
• Leaves: 225
• Category: Library

✦ Synopsis

This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches.

The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. Thebook concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals.

✦ Table of Contents

Contents
List of Acronyms
1 Introduction
1.1 The Embedded Processor Landscape
1.1.1 Processors
1.1.2 Reconfigurable Logic
1.1.3 Processor Metrics
1.2 Processor Requirements for Embedded Processing
1.3 Architecture Proposal and Focus
1.4 Book Outline
1.5 Conclusions
References
2 CGRA Background and Related Work
2.1 Intrinsic Compute Efficiency
2.2 Definition of CGRAs
2.3 A History of CGRAs
2.3.1 DReaM (2000) [O]
2.4 CGRA Classification
2.4.1 Classification Legend
2.4.2 Classification
2.5 Observations on Past CGRAs
2.5.1 Our Research Guidelines
2.6 Conclusions
References
3 Concept of the Blocks Architecture
3.1 Separation of Data and Control
3.2 Network Structure
3.3 Memory Hierarchy
3.4 Configuration
3.5 Function Units
3.6 Construction of Architecture Instances
3.6.1 Constructing VLIW Processors
3.6.2 Constructing SIMD Processors
3.6.3 Application Specific Data-Paths
3.7 Multi-Processor, Communication, and Synchronization
3.7.1 Locking on Global Memory
3.7.2 Local Memory Sharing
3.7.3 Direct Inter-LSU Communication
3.7.4 DMA Controller
3.7.5 Synchronization via FIFO
3.7.6 Hiding Memory Latency
3.8 Function Unit Granularity
3.9 Approximate Computing
3.10 Conclusions
References
4 The Blocks Framework
4.1 Overview of the Blocks Tool-Flow
4.2 Design Parameters
4.2.1 Function Unit Types
4.2.2 Instruction Specification
4.2.3 Memory Sizes and Interface
4.2.4 User Architecture Specification
Specifying a Fixed Architecture
Specifying a Reconfigurable Architecture
4.3 Hardware Generation
4.3.1 The Compute Template
4.3.2 The Core Template
4.3.3 The Top Level Template and Test-Bench
4.4 Programming Blocks
4.5 Configuration and Binary Generation
4.5.1 Assembler
4.5.2 Bit-File Generator
4.5.3 Binary Generator
4.5.4 Automatic Placement and Routing Tool
4.6 Conclusions
References
5 Energy, Area, and Performance Evaluation
5.1 Architectures
5.1.1 Blocks Architecture Instance
5.1.2 Reference Architectures
Traditional CGRA
Application Specific Blocks Instances (Blocks-ASP)
ARM Cortex-M0
8-Lane SIMD with Control Processor
8-Issue Slot VLIW
5.1.3 Synthesis and Place and Route
5.1.4 Critical Path Analysis
5.2 Benchmark Kernels
5.3 Results
5.3.1 Reconfiguration Overhead of Blocks
Performance
Power and Energy
Area
5.3.2 Comparison with Fixed Architectures
Performance
Power and Energy
Area
Flexibility
5.4 Conclusions
References
6 Architectural Model
6.1 Micro-benchmarks
6.1.1 Input Vector and Program Sequence Generation
6.1.2 Obtaining Energy and Area Numbers
6.1.3 Energy and Area Estimation for Memories
6.2 Energy and Area Models
6.2.1 Model Requirements for Design Space Exploration
6.2.2 Energy Model
Computing Energy for Function Units
Computing Energy for Switch-Boxes
Computing Energy for the Arbiter
Computing Energy for the Memories
6.2.3 Area Model
6.3 Evaluation
6.3.1 Energy Model Evaluation
Energy Estimation for Hard-Wired Instances
Energy Estimation for Reconfigurable Instances
6.3.2 Area Model Evaluation
6.3.3 Model Calculation Time
6.4 Conclusions
References
7 Case Study: The BrainSense Platform
7.1 Background
7.1.1 Existing BCI Platforms
7.1.2 The BrainSense BCI Concept
7.2 System Level Design
7.2.1 Communication and Peripherals
7.2.2 The BrainSense Processor
7.2.3 Memory and Interconnect
7.3 Algorithm Analysis and Acceleration
7.4 Evaluating BrainSense Energy Consumption
7.5 Conclusions
References
8 Conclusions and Future Work
8.1 Conclusions
8.2 Future Work
References
A The Blocks Function Units
A.1 The Arithmetic Logic Unit (ALU)
A.2 The Accumulate and Branch Unit (ABU)
A.3 The Load–Store Unit (LSU)
A.4 The Multiplier Unit (MUL)
A.5 The Register File (RF)
A.6 The Immediate Unit (IU)
Reference
Index