✦ LIBER ✦
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
✍ Scribed by Jaiswal, Manish Kumar; Cheung, Ray C.C.
- Book ID
- 122497118
- Publisher
- Elsevier Science
- Year
- 2013
- Tongue
- English
- Weight
- 411 KB
- Volume
- 44
- Category
- Article
- ISSN
- 0026-2692
No coin nor oath required. For personal study only.