Architecture of highly parallel ap1000 computer

✍ Scribed by Hiroaki Ishihata; Toshiyuki Shimizu; Morio Ikesaka; Satoshi Inano; Morio Ikesaka

• Publisher: John Wiley and Sons
• Year: 1993
• Tongue: English
• Weight: 835 KB
• Volume: 24
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/scj.4690240707

✦ Synopsis

Abstract

This paper describes the architectural features of the AP1000 message‐passing computer. The architecture is designed to speed up barrier synchronization, data distribution and collection, broadcasting, and message handling. In recent message‐passing computers, the most significant communication overhead is that associated with interrupt processing and message assembly/disassembly, because the adoption of new routing schemes has reduced the network latency.

It is important for a fast message‐passing computer to reduce not only network latency but also message handling latency. Although broadcasting, data distribution and collection, and barrier synchronization are necessary functions in many applications, these functions were slow in prior message‐passing computers because each of these functions were simulated by many one‐to‐one communications. The AP1000 has three independent communication networks and message handling hardwares, fast barrier synchronization capabilities, and data distribution and collection hardware to speed up those functions.