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Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

✍ Scribed by Akarvardar, K.; Eggimann, C.; Tsamados, D.; Singh Chauhan, Y.; Wan, G.C.; Ionescu, A.M.; Howe, R.T.; Wong, H.-S.P.

Book ID: 111918395
Publisher: IEEE
Year: 2008
Tongue: English
Weight: 1004 KB
Volume: 55
Category: Article
ISSN: 0018-9383
DOI: 10.1109/ted.2007.911070

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