Analog IC Design Techniques for Nanopower Biomedical Signal Processing

✍ Scribed by Chutham Sawigun, Wouter A. Serdijn

• Publisher: River Publishers
• Year: 2022
• Tongue: English
• Leaves: 199
• Edition: 1
• Category: Library

✦ Synopsis

As the requirements for low power consumption and very small physical dimensions in portable, wearable and implantable medical devices are calling for integrated circuit design techniques using MOSFETs operating in the subthreshold regime, this book first revisits some well-known circuit techniques that use CMOS devices biased in subthreshold in order to establish nanopower integrated circuit designs. Based on the these findings, this book shows the development of a class-AB current-mode sample-and-hold circuit with an order of magnitude improvement in its figure of merit compared to other state-of-the-art designs. Also, the concepts and design procedures of 1) single-branch filters 2) follower-integrator-based lowpass filters and 3) modular transconductance reduction techniques for very low frequency filters are presented. Finally, to serve the requirement of a very large signal swing in an energy-based action potential detector, a nanopower class-AB current-mode analog multiplier is designed to handle input current amplitudes of more than 10 times the bias current of the multiplier circuit. The invented filter circuits have been fabricated in a standard 0.18 µ CMOS process in order to verify our circuit concepts and design procedures. Their experimental results are reported.

✦ Table of Contents

Cover
Half Title
Series Page
Title Page
Copyright Page
Table of Contents
Preface
List of Figures
List of Tables
1: Introduction
1.1 Motivations
1.1.1 Understanding the Human Nervous System
1.1.2 Paradigm Shift in Bio-Medicine
1.2 Analog Signal Processing in Wearableand Implantable Devices
1.3 Nanopower CMOS IC Design Challenges
1.4 Materials and Methods
1.5 Book Organization
2: Review of Relevant Techniques and MOSFET Model
2.1 Introduction
2.2 Switched-Current Technique
2.2.1 1st and 2nd-Generation SI Memory Cells
2.2.2 Switching Error Cancellation in a SI Memory Cells
2.3 Gm − C Filters
2.3.1 Basic Concept and Design Considerations
2.3.2 Power-Efficient Gm – C Filters
2.4 Translinear Circuits
2.4.1 TL Principle
2.4.2 Exponential and sinh Transconductors
2.4.3 Current-Mode Analog Multiplier
2.5 EKV MOS Model for Low-Current Analog Design
2.5.1 Large-Signal Equations
2.5.2 Small-Signal Model
2.6 Conclusions
Part I: Analog Sampled-Data Circuit Technique
3: Switched-Current Technique in Subthreshold CMOS
3.1 Introduction
3.2 Feedback Analysis of a 2nd-Generation SI Memory Cell
3.2.1 Reexamination of a 2nd-Generation SI Memory Cell
3.2.2 Reconsideration of the Performance Enhancement Techniques
3.2.3 Stability and Transient Behavior
3.3 Design Consideration: Class-A and Class-AB
3.3.1 Current Consumption
3.3.2 Signal Excursion and Drivability
3.3.3 Noise
3.3.4 Effects of Transistor Mismatch, Input Current Imbalance and Switching Error Cancellation
3.3.5 Supply Noise Rejection
3.4 Conclusions
4: A Class-AB Current-Mode Subthreshold SH Circuit
4.1 Introduction
4.2 Design of a Class-AB CSH Circuit
4.2.1 Bias Condition
4.2.2 Input Current Limitation and Settling Behavior
4.3 Circuit Simulations
4.4 Conclusions
Part II: Compact Continuous-Time Filters
5: Nanopower BPF Using Single-Branch Biquads
5.1 Introduction
5.2 Single Branch Filters
5.2.1 Filter Topology Using Feedback Transconductors
5.2.2 Supply Voltage Requirement and Current Consumption
5.2.3 Noise
5.3 Cascaded Bandpass Filter
5.3.1 Filter Topology Considerations
5.3.2 Transistor Level Realization
5.3.3 Dynamic Range
5.3.4 Common-Mode Behavior
5.4 Design Methodology
5.4.1 Filter Order
5.4.2 Midband Gain and Dynamic Range
5.4.3 Center Frequency, Bias Current and Tuning
5.4.4 Transistor Dimensions
5.5 Measurement Results
5.6 Conclusions
6: Follower-Integrator-Based LPF for ECG Detection
6.1 Introduction
6.2 ECG Detector LPF Design
6.3 Follower-Integrator-based Lowpass Filter
6.3.1 Concept
6.3.2 Transistor-Level Consideration
6.4 ECG Lowpass Filter Design
6.4.1 Filter Topology
6.4.2 Supply Voltage Requirement, Signal Swing and Tuning
6.4.3 Signal-to-Noise Ratio
6.4.4 Supply Noise Rejection and Stability
6.5 Design Procedure
6.5.1 Dynamic Range
6.5.2 Cutoff Frequency, Bias Current and Power Consumption
6.5.3 Tuning
6.5.4 Transistor Dimensions
6.6 Measurement Results
6.7 Conclusions
Part III: Very Low-Frequency Filtering and Large-Swing Multiplication
7: Transconductance Reduction Technique for VLF Filters
7.1 Introduction
7.2 Review of Transconductance Reduction Techniques
7.3 Wide-Linear Range Low-Gm Transconductor
7.3.1 Concept
7.3.2 Noise and Dynamic Range
7.3.3 Current Consumption and Circuit Complexity
7.4 Filter Design and its Measured Results
7.4.1 Butterworth 2nd-order LPF
7.4.2 Supply Voltage Requirement and Signal Swing
7.4.3 Design Procedure
7.4.3.1 Passband gain
7.4.3.2 Minimum bias current and number of stages
7.4.3.3 Recovering DR
7.4.3.4 Bias circuit
7.4.4 Measurement Results
7.5 Conclusions
8: Large-Swing Current Multiplier for AP Detection
8.1 Introduction
8.2 Class-AB Current Multiplier
8.3 Subthreshold Class-AB Building Blocks
8.4 Simulations
8.5 Conclusions
9: Conclusions and Future Work
9.1 General Conclusions
9.2 List of Achievements
9.3 Future Work
Appendix APhase-Locked Peak-Picking Speech Processor
A.1 Introduction
A.2 Speech Processing in Cochlear Implants
A.3 Review and Comparison of Existing Processing Strategies
A.3.1 Continuous Interleaved Sampling
A.3.2 Zero-Crossing Detection
A.3.3 Peak-Picking Technique
A.3.4 Race-to-Spike Asynchronous Interleaved Sampling
A.4 System Simulations
A.5 Discrete-Time Peak-Instant Detector
A.5.1 Switched-Current PID Concept
A.5.2 Switched-Current PID Circuit
A.5.3 Circuit Simulation
A.6 Discussion and Conclusions
Appendix B: Harmonic Distortion Calculation for Chapter 3
B.1 Class A CSH Circuit
B.2 Class-AB CSH Circuit
References
Index
About the Authors