This research explores a compressed memory hierarchy model which can increase both the eective memory space and bandwidth of each level of memory hierarchy. It is well known that decompression time causes a critical eect to the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed memory systems. This paper proposes a selective compressed memory system (SCMS) incorporating the compressed cache architecture and its management method. To reduce or hide decompression overhead, this SCMS employs several eective techniques, including selective compression, parallel decompression and the use of a decompression buer. In addition, ยฎxed memory space allocation method is used to achieve ecient management of the compressed blocks. Trace-driven simulation shows that the SCMS approach can not only reduce the on-chip cache miss ratio and data trac by about 35% and 53%, respectively, but also achieve a 20% reduction in average memory access time (AMAT) over conventional memory systems (CMS). Moreover, this approach can provide both lower memory trac at a lower cost than CMS with some architectural enhancement. Most importantly, the SCMS is a more attractive approach for future computer systems because it oers high performance in cases of long DRAM latency and limited bus bandwidth.