An improved Elmore delay model for VLSI interconnects
β Scribed by Mutlu Avci; Serhan Yamacli
- Publisher
- Elsevier Science
- Year
- 2010
- Tongue
- English
- Weight
- 512 KB
- Volume
- 51
- Category
- Article
- ISSN
- 0895-7177
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π SIMILAR VOLUMES
State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described
This letter proposes the substructure-front S-F technique in conjunction with the geometry-independent measured equation of ( ) in¨ariance GIMEI for fast parameter extraction of a multilayer and ( ) multiconductor interconnect based on the finite-element method FEM for VLSI circuit analysis. Results