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An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

✍ Scribed by Diaz, C.H.; Hun-Jan Tao, ; Yao-Ching Ku, ; Yen, A.; Young, K.


Book ID
120824728
Publisher
IEEE
Year
2001
Tongue
English
Weight
65 KB
Volume
22
Category
Article
ISSN
0741-3106

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