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An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

✍ Scribed by Shrutisagar Chandrasekaran; Abbes Amira; Shi Minghua; Amine Bermak


Book ID
107391278
Publisher
Springer-Verlag
Year
2008
Tongue
English
Weight
735 KB
Volume
3
Category
Article
ISSN
1861-8200

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An efficient algorithm for implementing the finite-element ( ) time-domain FETD method on parallel computers is presented. An unconditionally stable implicit FETD algorithm is combined with the ( ) finite-element tearing and interconnecting FETI method. This domain decomposition algorithm con¨erges