Most commercial asynchronous transfer mode (ATM) switches are of the shared-medium type and are based on the well-known TDMA bus arbitration scheme. This is primarily due to the ease of implementation of shared-medium switches. However, ATM switches of this category, suffer from a major drawback Ð they are not scalable for large sizes because they require a bus running N times faster than the ports (where N is the switch size, i.e. the number of input ports). Furthermore, ATM switches that are based on the TDMA bus arbitration scheme suffer from low performance when the offered traf®c is bursty. In this paper, a new approach to the design of scalable shared-medium ATM switches, which are capable of operating ef®ciently under bursty traf®c, is introduced. The main features of the proposed switch are the following: (1) It uses the broadcast bus topology. ( 2) There is no need to have a bus running N times faster than the ports. A bus of any bandwidth can be used. (3) It uses a fully distributed bus arbitration scheme. (4) The MAC algorithm, which is implemented at each input port has a time complexity, which is in the nanoseconds range and is independent of the switch size N. (5) It is capable of operating ef®ciently under bursty traf®c conditions. ( 6) It is based on the use of learning automata in order to allocate the bandwidth to the input ports according to their needs.