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An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

✍ Scribed by M. Renovell; J.M. Portal; J. Figueras; Y. Zorian

Book ID: 110262760
Publisher: Springer US
Year: 2000
Tongue: English
Weight: 124 KB
Volume: 16
Category: Article
ISSN: 0923-8174
DOI: 10.1023/a:1008355701933

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