Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point D
โฆ LIBER โฆ
[ACM Press the 4th international conference - Seoul, Korea (2006.10.22-2006.10.25)] Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06 - SHAPES:
โ Scribed by Paolucci, Pier S.; Jerraya, Ahmed A.; Leupers, Rainer; Thiele, Lothar; Vicini, Piero
- Book ID
- 121724881
- Publisher
- ACM Press
- Year
- 2006
- Tongue
- English
- Weight
- 436 KB
- Category
- Article
- ISBN-13
- 9781595933706
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