Accelerating test, validation and debug of high speed serial interfaces

✍ Scribed by Fan, Yongquan;Fan, Yongquan

• Publisher: Springer
• Year: 2010;2011
• Tongue: English
• Leaves: 202
• Category: Library

✦ Synopsis

This practical text presents industry-trialed methods for the testing of HSSIs, speeding up testing by a factor of 1000. The testing of both transmission and reception are dealt with in detail, with special emphasis put on performance under injected jitter.

✦ Table of Contents

6.2.1.1 One Bit Random .umber Generator......Page 7
5.2.3. HSSI Testing Demonstration......Page 9
Cover......Page 1
6.1.1.2 Box-Muller Method......Page 2
6.1.2 Our Method......Page 5
5.2.1 Implementing a Serial BERT......Page 6
Acknowledgments......Page 8
6.1.1.4 Cellular Automata Based Method......Page 4
Index......Page 11
2.2.2 Jitter and BER......Page 13
6.2.2.3 Accuracy Improvement......Page 16
1.1.2 Qualification Challenges......Page 18
6.3.2 S&R Setting......Page 23
2.1 High-Speed Serial Communication......Page 24
1.1.1 HSSI Technology Trends......Page 15
1.1.3 ATE Perspectives......Page 19
6.2.3.2 Kurtosis Value......Page 20
1.2 Contributions......Page 21
4.3.5 Limitations of Each Approach......Page 25
6.4 Advantages of Our AWG. Generator......Page 28
2.1.2 BER Mechanisms......Page 29
4.4.4 Impact of the Reference Clock......Page 30
4.4.5 Extending to 6 Gbps Applications......Page 31
2.1.3 Jitter and &oise Impacts to BER......Page 32
3.4.1 Jitter Tolerance Extrapolation Algorithm......Page 33
2.2.2 Jitter and BER......Page 36
3.4.3 Accelerating Jitter Tolerance Compliance Testing......Page 43
3.4.4 Discussion......Page 45
2.3.2 Simulation and Emulation......Page 46
3.5.2 CDR Characteristics Analysis......Page 48
6.1.1.3 Mixed Method......Page 3
6.2.2.1.2 FIFO Implementation......Page 12
1.1 Motivation......Page 14
6.2.3.1 Q(x) Evaluation......Page 17
1.3 Overview of the Book......Page 22
5.4.3 Limitations and Further Considerations......Page 26
2.1.1 HSSI Structure......Page 27
Table of Contents......Page 10
2.2.1 Jitter Overview......Page 34
2.2.3 Jitter Testing......Page 39
2.3.1 BER and S&R......Page 41
2.3.3 AWG& Emulation......Page 47
3 Accelerating Receiver Jitter Tolerance Testing on ATE......Page 49
3.1.1 Receiver Structure and Characteristics......Page 50
3.1.2 Jitter Tolerance Testing Overview......Page 56
3.1.3 Proposed &ew Method......Page 59
3.2 Jitter Test Signal Generation......Page 63
3.2.1 Choosing Test Signal Parameters......Page 64
3.2.2 Periodic Jitter Injection......Page 66
3.2.2.1 Creating Jitter-Free Data Signal......Page 67
3.2.2.3 Modulating the Data Signal......Page 68
3.2.2.4 Generating Bandwidth Limited Signals......Page 69
3.2.2.5 Downsampling to Get AWG Samples......Page 71
3.2.3 Fractional Sampling......Page 72
3.2.4 Jitter Calibration......Page 73
3.2.5 Random Jitter Control......Page 76
3.3 Receiver Bit Error Monitoring......Page 77
3.3.1 ATE-based Error Detection......Page 78
3.3.2 DFT-based Error Detection......Page 79
3.4 Jitter Tolerance Extrapolation......Page 80
3.4.1 Jitter Tolerance Extrapolation Algorithm......Page 81
3.4.2 Accelerating Jitter Tolerance Characterization......Page 84
3.4.3 Accelerating Jitter Tolerance Compliance Testing......Page 91
3.4.4 Discussion......Page 93
3.5.1 Jitter Transfer Characterization......Page 94
3.5.2 CDR Characteristics Analysis......Page 96
4.1 Introduction......Page 98
4.1.1 Transmitter Jitter Testing Overview......Page 99
4.1.2 Proposed Solution......Page 100
4.2.1 Overview of the Test Setup......Page 101
4.2.2 Principles of Clock Settings......Page 102
4.2.3 Test Setting Parameter Calculations......Page 104
4.3. Jitter Extraction......Page 108
4.3.1 Generating Edge Displacement......Page 109
4.3.2 Time Domain Approach......Page 111
4.3.2.2 DJ Extraction......Page 113
4.3.2.3TJ Calculation......Page 114
4.3.3.1 RJ Extraction......Page 118
4.3.3.2 DJ Extraction......Page 119
4.3.4 Hybrid Approach......Page 120
4.3.5 Limitations of Each Approach......Page 122
4.4 Experimental Results......Page 123
4.4.2 Correlating Two RJ Approaches......Page 124
4.4.3 Impact of Test Patterns......Page 126
4.4.4 Impact of the Reference Clock......Page 127
4.4.5 Extending to 6 Gbps Applications......Page 128
4.5 Summary......Page 129
5 Testing HSSIs with or without ATE Instruments......Page 131
5.1.1 Internal BERT......Page 132
5.1.2 Internal Loopback......Page 133
5.1.3 Other DFT Techniques......Page 134
5.1.4 Limitations of DFTs......Page 135
5.2.1 Implementing a Serial BERT......Page 136
5.2.2 Implementing a Parallel BERT......Page 138
5.2.3. HSSI Testing Demonstration......Page 139
5.3.1 Testing Setup......Page 140
5.3.2 Phase Delay Based jitter Injection......Page 141
5.3.3 Experimental Results......Page 144
5.4 A Versatile HSSI Testing Scheme......Page 147
5.4.1.1 Testing, Validation and Debugging on ATE......Page 148
5.4.1.2 External Loopback with Jitter Injection......Page 149
5.4.1.3 Other Configurations......Page 150
5.4.2 High Speed Relays......Page 151
5.4.3 Limitations and Further Considerations......Page 156
6.1 AWG. Generation Overview......Page 158
6.1.1.1 CLT Method......Page 159
6.1.1.3 Mixed Method......Page 160
6.1.1.4 Cellular Automata Based Method......Page 161
6.1.1.5 Analog Method......Page 162
6.2.1.1 One Bit Random .umber Generator......Page 164
6.2.1.2 Multiple-Bit Random .umber Generator......Page 167
6.2.2.1 Implementing a Single Generator......Page 168
6.2.2.1.1 Generating 1 V and S......Page 169
6.2.2.1.3 Generating W......Page 171
6.2.2.1.4 Generating Outputs......Page 172
6.2.2.3 Accuracy Improvement......Page 173
6.2.3.1 Q(x) Evaluation......Page 174
6.2.3.2 Kurtosis Value......Page 177
6.3.1 Baseband Signal Formats......Page 178
6.3.2 S&R Setting......Page 180
6.3.3 Testing Setup and Results......Page 181
6.4 Advantages of Our AWG. Generator......Page 185
7 Conclusions......Page 188
Reference......Page 191
Index......Page 201