ABCs of z/OS System Programming

✍ Scribed by Paul Rogers, Alvaro Salla

• Publisher: IBM Corporation
• Year: 2012
• Tongue: English
• Leaves: 648
• Category: Library

✦ Table of Contents

Go to the current abstract on ibm.com/redbooks http://www.redbooks.ibm.com/abstracts/sg246990.html?Open&pdfbookmarkFront cover
Contents
Notices
Trademarks
Preface
The team who wrote this book
Chapter 1. Introduction to z/Architecture
1.1 Computer architecture overview
1.2 Concept of a process
1.3 Process states and attributes
1.4 System components
1.5 Processing units (PUs)
1.6 z/Architecture enhancements
1.7 64-bit address space map
1.8 Addressing mode
1.9 64-bit dynamic address translation
1.10 CP registers (general)
1.11 Floating point registers
1.12 Current program-status word (PSW)
1.13 Next sequential instruction address
1.14 Program-status-word format
1.15 Prefixed save area (PSA)
1.16 Several instruction formats
1.17 Microcode concepts
1.18 z/Architecture components
1.19 z/Architecture data formats
1.20 Interrupts
1.21 Interrupt processing
1.22 Types of interrupts
1.23 Supervisor call interrupt
1.24 Storage protection
1.25 Storage protection logic
1.26 Addresses and address spaces
1.27 z/Architecture address sizes
1.28 Storage addressing
1.29 Real storage locations
1.30 Dynamic address translation (DAT)
1.31 Dynamic address translation
1.32 Page faults
1.33 Dual address space (cross memory)
1.34 Access register mode (dataspaces)
1.35 CPU signaling facility
1.36 Time measurement TOD
1.37 Time measurement (CP timer)
1.38 Sysplex Timer expanded availability configuration
1.39 Server Time Protocol (STP)
1.40 Data center and I/O configuration
1.41 Channel subsystem (CSS) elements
1.42 Multiple CSS structure (z10 and z196 EC)
1.43 Control units
1.44 Device number
1.45 Subchannel number
1.46 Subchannel numbering
1.47 Control unit address
1.48 Unit addresses
1.49 Map device number to device address
1.50 Multiple channel paths to a device
1.51 Start subchannel (SSCH) logic
1.52 SAP PU logic
1.53 Channel processing
1.54 I/O interrupt processing
1.55 I/O summary
Chapter 2. Introducing the IBM z10
2.1 z196 and z10 overview
2.2 IBM System z nomenclature
2.3 z10 EC naming summary
2.4 The power of GHz (high frequency)
2.5 Processor unit (PU) instances
2.6 z10 EC hardware model
2.7 z10 EC sub-capacity models
2.8 z10 EC frames and cages
2.9 Book topology comparison
2.10 NUMA topology
2.11 z10 EC Books
2.12 Multi-chip module (MCM)
2.13 PU chip
2.14 Book element interconnections
2.15 Pipeline in z10 EC
2.16 Pipeline branch prediction
2.17 About each z10 EC PU
2.18 z10 EC storage controller (SC) chip
2.19 Recapping the z10 EC design
2.20 Three levels of cache
2.21 Software/hardware cache optimization
2.22 HiperDispatch considerations
2.23 Central storage design
2.24 Addresses and addresses
2.25 Hardware system area (HSA)
2.26 Large page (1 M) support
2.27 Connecting PU cage with I/O cages
2.28 Detailed connectivity
2.29 HCA and I/O card connections
2.30 InfiniBand interconnect technology
2.31 I/O cage
2.32 The I/O data flow
2.33 Redundant I/O Interconnect
2.34 z10 EC I/O features supported
2.35 16-port ESCON channel card
2.36 FICON features and extended distance
2.37 Features in z10 and z196
2.38 z10 EC new features
Chapter 3. Introducing the IBM zEnterprise
3.1 zEnterprise overview
3.2 Migrating Unix/Linux workloads back to the mainframe
3.3 z196 numeric comparison
3.4 Processor Units (PU) instances
3.5 z196 models
3.6 Sub capacity models
3.7 Model capacity identifier and MSU/h
3.8 z196 frames, cages and I/O drawers (I)
3.9 z196 frames, cages and I/O drawers (II)
3.10 NUMA topology
3.11 z196 books
3.12 Any to any book connectivity
3.13 Fanout cards in a book
3.14 Multichip module (MCM)
3.15 Frequency (GHz) in a z196 PU
3.16 Quad core PU chip
3.17 PU chip coprocessor
3.18 Storage controller (SC) chip in MCM
3.19 z196 book recapping
3.20 Pipeline concept within a PU
3.21 Out of order execution
3.22 z196 instructions
3.23 Non-quiesce SSKE instruction
3.24 z10 EC and z196 cache design comparison
3.25 Storage layers
3.26 z196 cache design (I)
3.27 z196 cache design (II)
3.28 HiperDispatch concepts
3.29 The clerk dilemma
3.30 z/OS dispatcher logic in HiperDispatch
3.31 Central Storage design
3.32 MCUs and DIMMs in a z196 book
3.33 Purchase memory offerings
3.34 Addresses and addresses
3.35 Hardware system area (HSA)
3.36 Large pages
3.37 An I/O data flow tree analogy
3.38 Book to channel connectivity
3.39 Connecting books with I/O channels
3.40 FICON I/O card
3.41 FICON channel topics in z196
3.42 I/O cage
3.43 I/O drawer
3.44 Redundant I/O interconnect
3.45 Coupling Facility links
3.46 Infiniband protocol
3.47 z196 maximum number of channel per type
3.48 z/OS discovery and auto-configuration (zDAC)
3.49 WWPN and fabrics discovery
3.50 zDAC software and hardware requirements
3.51 zDAC policy in HCD
3.52 zDAC policy
3.53 zDAC discovered HCD panel
3.54 zDAC proposed HCD panel
3.55 Logical channel subsystem
3.56 LP ID, MIF ID, and spanning concepts
3.57 Physical channel ID (PCHID)
3.58 Association between CHPID and PCHID
3.59 Comparison between System z servers
3.60 IOCP statements example
3.61 Configuration definition process
3.62 Channel availability features
3.63 Introduction to MIDAW
3.64 Channel command word (CCW) concept
3.65 CCWs and virtual storage - IDAW Concept
3.66 DASD extended format
3.67 Using MIDAWs
3.68 Reducing CCWs using MIDAW
3.69 MIDAW performance results
3.70 Cryptography concepts
3.71 Cryptography in z196
3.72 z196 crypto synchronous functions
3.73 Crypto express-3
3.74 z196 crypto asynchronous functions
3.75 Protected keys in CPACF
3.76 PR/SM and cryptography
3.77 Just-in-time concurrent upgrades
3.78 On/Off capacity on demand (CoD)
3.79 Other capacity upgrade plans
3.80 Capacity provisioning
3.81 Capacity provisioning domain
3.82 SNMP interface to HMC
Chapter 4. zEnterprise BladeCenter Extension Model 002 (zBX)
4.0.1 zEnterprise
4.1 zBX hardware rack components
4.2 BladeCenter chassis
4.3 Blades by function
4.4 The blade types
4.5 Blades data warehouse roles
4.6 POWER7 blades
4.7 WebSphere datapower appliance blades
4.8 Nodes and ensembles
4.9 zBX networking and connectivity
4.10 Hardware management consoles (HMC)
Chapter 5. z/Enterprise Unified Resource Manager
5.1 Unified resource manager introduction
5.2 Refreshing the ensemble concept
5.3 zManager location in zEnterprise
5.4 zManager major roles
5.5 zManager hypervisors and energy
5.6 Energy SAD frame
5.7 More details about energy management
5.8 Energy data available from HMC
5.9 Systems director active energy manager
5.10 zManager operations control
5.11 Change management functions
5.12 Problem management
5.13 Configuration management
5.14 zManager HMC configuration panel
5.15 Operations management
5.16 Performance monitoring and business management
5.17 Ensemble management
5.18 zManager performance, virtual life cycle and networks
5.19 Network management
5.20 zEnterprise platform performance manager
5.21 PPM virtual servers
5.22 Virtual server definition
5.23 z/OS WLM main terms
5.24 Intelligent resource director review
5.25 RD for a zLinux logical partition
5.26 RMF and IRD zLinux implementation
5.27 PPM wizard welcome panel
5.28 PPM components
5.29 Differences between PPM and z/OS WLM
5.30 PPM agents
5.31 Application response measurement (ARM)
5.32 Virtual server processor management (I)
5.33 Virtual server CPU management (II)
5.34 PPM major constructs
5.35 PPM workload concepts
5.36 PPM workload definition
5.37 PPM policy
5.38 Service class concepts
5.39 Service class definition
5.40 Classification rules
5.41 z/OS WLM agent
5.42 Connecting PPM SC with a WLM service class
5.43 z/VM agent role in PPM
5.44 PowerVM agent role in PPM
5.45 PPM performance data reporting
Chapter 6. System z connectivity
6.1 Connectivity overview
6.2 Multiple Image Facility channels
6.3 Channel subsystem connectivity
6.4 CSS configuration management
6.5 Displaying channel types
6.6 ESCON architecture
6.7 ESCON concepts
6.8 ESCD (switch) functions
6.9 ESCON Director (ESCD) description
6.10 ESCON Director matrix
6.11 Channel-to-channel adapter
6.12 ESCON CTC support
6.13 FICON channels
6.14 FICON conversion mode
6.15 Supported FICON native topologies
6.16 Fibre Channel Protocol (FCP)
6.17 FICON improvements (1)
6.18 FICON improvements (2)
6.19 FICON/ESCON numerical comparison
6.20 FICON switches
6.21 Cascaded FICON Directors
6.22 FICON Channel to Channel Adapter (FCTC)
6.23 z9 Coupling Facility links
6.24 z10 EC Coupling Facility connectivity options
6.25 All z10 EC coupling link options
6.26 OSA-Express
6.27 QDIO architecture
6.28 HiperSockets connectivity
6.29 Hardware Configuration Definition (HCD)
Chapter 7. Virtualization and Logical Partition (LPAR) concepts
7.1 Virtualization definitions
7.2 Virtualization concepts
7.3 Virtualized physical resources
7.4 Hypervisor types
7.5 Hypervisor technologies (I)
7.6 Hypervisor technologies (II)
7.7 IBM hypervisors
7.8 z/Virtual Machine (z/VM)
7.9 z/VM options in HMC
7.10 Virtualization in zBX blades
7.11 PowerVM virtual servers
7.12 Comparing hypervisor terminology
7.13 History of operating environments
7.14 CPC in basic mode
7.15 CPC in LPAR mode
7.16 Shared and dedicated logical CPs example
7.17 LPAR dispatching and shared CPs
7.18 Reasons for intercepts
7.19 LPAR event-driven dispatching
7.20 LPAR time slice interval
7.21 LPAR weights
7.22 z196 PU pools
7.23 Capping workloads
7.24 Types of capping
7.25 LPAR capping
7.26 LPAR capped versus uncapped
7.27 Soft capping
7.28 Group capacity in soft capping
7.29 Intelligent resource director (IRD)
7.30 WLM LPAR CPU management
7.31 Intelligent Resource Director benefits
7.32 WLM concepts
7.33 Dynamic Channel Path Management (DCM)
7.34 Channel subsystem I/O priority queueing
Chapter 8. Hardware Configuration Definition (HCD)
8.1 What is HCD
8.2 IOCP example
8.3 IOCP elements
8.4 Hardware and software configuration
8.5 HCD functions
8.6 Dynamic I/O reconfiguration
8.7 Dynamic I/O reconfiguration device types
8.8 IODF data set
8.9 Definition order
8.10 HCD primary menu
8.11 Creating a new work IODF
8.12 Defining configuration data
8.13 Operating system definition
8.14 Defining an operating system
8.15 EDT and esoterics
8.16 How to define an EDT (1)
8.17 How to define an EDT (2)
8.18 Defining an EDT identifier
8.19 How to add an esoteric
8.20 Adding an esoteric
8.21 Defining switches
8.22 Adding switches
8.23 Defining servers
8.24 Information for defining a server
8.25 Defining a server
8.26 Working with LCSSs
8.27 Logical channel subsystems defined
8.28 Adding a logical partition (LP)
8.29 z9 EC LPAR server configuration
8.30 Channel operation mode
8.31 Channel types
8.32 Information required to add channels
8.33 Working with channel paths
8.34 Adding channel paths dynamically
8.35 Adding a channel path
8.36 Defining an access and a candidate list
8.37 Adding a control unit
8.38 Information required to define a control unit
8.39 Adding a control unit
8.40 Defining a 2105 control unit
8.41 Selecting a processor/control unit
8.42 Servers and channels for connecting control units
8.43 Defining server attachment data
8.44 Information required to define a device
8.45 z/OS device numbering
8.46 Defining a device
8.47 Defining device CSS features (1)
8.48 Defining device CSS features (II)
8.49 Defining devices to the operating system
8.50 Defining operating system device parameters
8.51 Assigning a device to an esoteric
8.52 Defining an NIP console
8.53 Using the CHPID mapping tool
8.54 Build a production IODF
8.55 Define the descriptor fields
8.56 Production IODF created
8.57 Activating a configuration with HCD
8.58 View an active IODF with HCD
8.59 Viewing an active IODF
8.60 Displaying device status
8.61 HCD reports
8.62 Hardware Configuration Manager (HCM)
Chapter 9. DS8000 series concepts
9.1 DASD controller capabilities
9.2 DS8000 characteristics
9.3 DS8000 design
9.4 Internal fabric and I/O enclosures
9.5 Disk subsystem
9.6 Switched Fibre Channel Arbitrated Loop (FC-AL)
9.7 Redundant array of independent disks (RAID)
9.8 DS8000 types of RAID
9.9 Logical subsystem (LSS)
9.10 Logical partition (LPAR)
9.11 Copy services classification criteria
9.12 Consistency group concept
9.13 Copy services in DS8000
9.14 FlashCopy
9.15 Consistency group in FlashCopy
9.16 Remote Mirror and Copy (example: PPRC)
9.17 Consistency groups in Metro Mirror
9.18 Global Copy (example: PPRC XD)
9.19 Global Mirror (example: async PPRC)
9.20 z/OS Global Mirror (example: XRC)
9.21 Parallel access volume (PAV)
9.22 HyperPAV feature for DS8000 series
9.23 HyperPAV and IOS
9.24 HyperPAV implementation
9.25 Display M=DEV command
9.26 RMF DASD report
9.27 RMF I/O Queueing report
9.28 DS8000 Capacity on Demand
9.29 DS command line interface (CLI)
9.30 Storage Hardware Management Console (S-HMC)
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