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A transputer-based gate-level fault simulator

โœ Scribed by G. Cabodi; S. Gai; M. Sonza Reorda


Book ID
104178964
Publisher
Elsevier Science
Year
1990
Weight
418 KB
Volume
30
Category
Article
ISSN
0165-6074

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This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the simulation speed and the parallel pattern strategy