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A three-dimensional, physically based compact model for IC VDMOS transistors

✍ Scribed by James Victory; Colin C. McAndrew; Rainer Thoma

Publisher
Elsevier Science
Year
1998
Tongue
English
Weight
628 KB
Volume
29
Category
Article
ISSN
0026-2692

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✦ Synopsis

A three-dimensional VDMOS model has been derived and implemented in SPICE. The model was developed and characterized for the square cell, rectangular grid device layout for Motorola's SmarTMOS TM technologies. The model includes physical models for RDSo. over gate voltage, temperature and cell number. It also includes accurate, scalable models for the gate-charge, including the voltage-varying gatedrain capacitance and the distributed effects of the buried layer and interconnect metal resistances on the total on-resistance of the device. This allows efficient and accurate modeling of typical VDMOS layouts.

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