✦ LIBER ✦

A systolic VSLI chip for implementing orthogonal transforms

✍ Scribed by Burleson, W.P.; Scharf, L.L.; Gabriel, A.R.; Endsley, N.H.

Book ID: 119773747
Publisher: IEEE
Year: 1989
Tongue: English
Weight: 451 KB
Volume: 24
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.18610

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design of efficient architectures for di

Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures

✍ Amira, A.; Bouridane, A.; Milligan, P.; Belatreche, A. 📂 Article 📅 2002 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 221 KB

Systolic Architecture for Implementation

Systolic Architecture for Implementation of 2-D Discrete Sine Transform

✍ M.N. Murty; S.S. Nayak; B. Padhy; S.N. Panda 📂 Article 📅 2012 🏛 Elsevier 🌐 English ⚖ 761 KB

Multidimensional systolic arrays for the

Multidimensional systolic arrays for the implementation of discrete Fourier transforms

✍ Hyesook Lim; Swartzlander, E.E., Jr. 📂 Article 📅 1999 🏛 IEEE 🌐 English ⚖ 367 KB

A residue number system implementation o

A residue number system implementation of real orthogonal transforms

✍ Dimitrov, V.S.; Jullien, G.A.; Miller, W.C. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 367 KB

Implementation of a New Orthogonal Shuff

Implementation of a New Orthogonal Shuffled Block Transform for Image Coding Applications

✍ Erdal Yazıcıoğlu; Sina Balkır; Günhan Dündar; Hakan Çağlar 📂 Article 📅 2000 🏛 Elsevier Science 🌐 English ⚖ 321 KB

his paper presents the implementation of a novel transform technique for two dimensional coding. The hardware is composed of six blocks, of which only three are distinct. The ``butter¯y'' block is the main engine of the transformer and is multiplier free. The matrix transposer block is a novel struc

A bit level systolic array for Walsh-Had

A bit level systolic array for Walsh-Hadamard transforms

✍ Long-Wen Chang; Ming-Chang Wu 📂 Article 📅 1993 🏛 Elsevier Science 🌐 English ⚖ 400 KB