A Synergistic Framework for Hardware IP Privacy and Integrity Protection

✍ Scribed by Meng Li, David Z. Pan

• Publisher: Springer
• Year: 2020
• Tongue: English
• Leaves: 147
• Edition: 1st ed. 2020
• Category: Library

✦ Synopsis

This book proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined to provide a formal security guarantee.

✦ Table of Contents

Preface
Contents
Acronyms
1 Introduction
1.1 Hardware IP Privacy and Integrity Challenges
1.2 Overview of This Book
References
2 Practical Split Manufacturing Optimization
2.1 Introduction
2.2 Preliminary
2.2.1 Attack Model of Untrusted Foundries
2.2.2 Motivating Example
2.2.3 State-of-the-Art Split Manufacturing Flow
2.3 Split Manufacturing Security Analysis
2.4 k-Security Realization
2.5 Practical Framework for Trojan Prevention
2.5.1 MILP-Based FEOL Generation
2.5.2 Lagrangian Relaxation Algorithm
Minimum-Cost Flow Transformation
Lagrangian Multiplier Update
2.5.3 k-Secure Layout Refinement
2.6 Experimental Results
2.6.1 Experimental Setup
2.6.2 FEOL Generation Strategy Comparison
2.6.3 Physical Synthesis Comparison
2.6.4 Physical Proximity Examination
2.6.5 Relation Between Overhead and Framework Parameters
2.7 Summary
References
3 IC Camouflaging Optimization and Evaluation
3.1 Introduction
3.2 ``Arms Race'' Evolution
3.3 Provably Secure IC Camouflaging
3.3.1 Preliminary: Active Learning
3.3.2 IC Camouflaging Security Analysis
3.3.3 Novel Camouflaging Cell Design
XOR-Type Cell Camouflaging Strategy
STF-Type Cell Camouflaging Strategy
Discussion
3.3.4 AND-Tree Camouflaging Strategy
Security Analysis of the AND-Tree Structure
AND-Tree Structure in General Circuits
Input Bias Evaluation
Tree Decomposability Characterization
3.3.5 Provably Secure IC Camouflaging
AND-Tree Detection in Original Netlist
Stochastic Greedy AND-Tree Insertion
AND-Tree Camouflaging Against Removal Attack
Comparison Between State-of-the-Art Techniques
3.3.6 Experimental Results
Verification of Camouflaging Cell Generation Strategy
Evaluation of AND-Tree Based Camouflaging Strategy
Impact of Structural and Functional Camouflaging
Effectiveness of Combination of Two Camouflaging Strategies
3.3.7 Summary
3.4 De-camouflaging Timing-Based Logic Obfuscation
3.4.1 Preliminary: Timing-Based Camouflaging
3.4.2 A Motivating Example
3.4.3 TimingSAT Framework
TU Insertion
Determine Input Query Through Unrolling
Netlist Simplification for De-camouflaging Acceleration
Key Post-processing
Discussion
3.4.4 Experimental Results
Efficiency of TimingSAT
Runtime Dependency of TimingSAT
Impact of Unrolling Time Frames
De-camouflaging of Combination of Timing-Based and Traditional Strategy
3.4.5 Summary
References
4 Fault Attack Protection and Evaluation
4.1 Introduction
4.2 Practical PPUF Design
4.2.1 Preliminaries
PPUF-Based Protocol
Max-Flow Problem in Directed Graph
Signal Delay in General Circuit
4.2.2 PPUF Topology and ESG Analysis
PPUF Topology and Basic Building Block
Lower Bound of PPUF Simulation
Upper Bound of PPUF Execution
ESG Amplification
Speeding Up Verifier's Task
4.2.3 PPUF Physical Realization
Complete Crossbar Structure
Interleaving Crossbar Placement
Input Challenge Pre-pruning
4.2.4 Experimental Results
Verification of Simulation Model and ESG
Verification of PPUF Practicality
PPUF Statistical Evaluation
Model-Building Attack Resilience
4.2.5 Summary
4.3 Cross-Level Monte Carlo Evaluation Framework
4.3.1 Motivation
4.3.2 Problem Formulation
Attack Model
Holistic Fault Injection Modeling
System Security Factor
4.3.3 Importance Sampling via System Pre-characterization
4.3.4 Cross-Level Fault Propagation Simulation
RTL-Level Golden Simulation
RTL-Level Fault Attack Simulation
Gate-Level Fault Attack Modeling
4.3.5 Experimental Results
4.3.6 Summary
References
5 Conclusion and Future Work
Index