✦ LIBER ✦

A Real-Time Edge Detector: Algorithm and VLSI Architecture

✍ Scribed by Fahad M. Alzahrani; Tom Chen

Publisher: Elsevier Science
Year: 1997
Tongue: English
Weight: 698 KB
Volume: 3
Category: Article
ISSN: 1077-2014
DOI: 10.1006/rtim.1996.0071

No coin nor oath required. For personal study only.

✦ Synopsis

Algorithm and VLSI Architecture

n this paper we present a very large scale integration (VLSI) architecture of a new edge detection algorithm, which has a very regular computational structure. The new algorithm detects Iweak edges and produces single-pixel localized edges. Due to its highly pipelined structure, the VLSI implementation of the algorithm outputs one edge-pixel every clock cycle. The VLSI architecture is a complete realization of the algorithm, where no degradation is introduced to the ASIC output when compared to edges produced by the algorithm. The detector is capable of processing video graphic array (VGA) sized images at 30 frames/s at a clock rate of 10 MHz in a stand-alone mode, where no additional glue logic is required. The ASIC was laid out and fabricated using Samsung's 0.8µm double-metal CMOS process.

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