✦ LIBER ✦

A programmable systolic trigger processor for FERA bus data

✍ Scribed by G. Appelquist; B. Hovander; B. Selldén; C. Bohm

Publisher: Elsevier Science
Year: 1993
Tongue: English
Weight: 751 KB
Volume: 327
Category: Article
ISSN: 0168-9002
DOI: 10.1016/0168-9002(93)90715-t

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A programmable systolic array correlator

A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

✍ R. Männer 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 437 KB

This paper describes a systolic array processor for a ring image Cherenkov Counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 ss. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements

A Fastbus module for trigger application

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

✍ P. Battaiotto; A. Colavita; F. Fratnik; L. Lanceri 📂 Article 📅 1991 🏛 Elsevier Science 🌐 English ⚖ 291 KB