A Parallel Implementation of a Fast Mult
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Yanhong Yuan; Prith Banerjee
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Article
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2001
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Elsevier Science
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English
β 396 KB
Very fast and accurate 3-D capacitance extraction is essential for interconnect optimization in VLSI ultra-deep sub-micron designs (UDSM). Parallel processing provides an approach to reducing the simulation turn-around time. This paper examines the parallelization of the well-known fast multipole-ba